{"id":"https://openalex.org/W2162180547","doi":"https://doi.org/10.1109/iscas.2005.1466066","title":"Fast Integer Linear Programming Based Models for VLSI Global Routing","display_name":"Fast Integer Linear Programming Based Models for VLSI Global Routing","publication_year":2005,"publication_date":"2005-07-27","ids":{"openalex":"https://openalex.org/W2162180547","doi":"https://doi.org/10.1109/iscas.2005.1466066","mag":"2162180547"},"language":"en","primary_location":{"id":"doi:10.1109/iscas.2005.1466066","is_oa":false,"landing_page_url":"https://doi.org/10.1109/iscas.2005.1466066","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2005 IEEE International Symposium on Circuits and Systems","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5080379451","display_name":"Laleh Behjat","orcid":"https://orcid.org/0000-0002-8122-0990"},"institutions":[{"id":"https://openalex.org/I168635309","display_name":"University of Calgary","ror":"https://ror.org/03yjb2x39","country_code":"CA","type":"education","lineage":["https://openalex.org/I168635309"]}],"countries":["CA"],"is_corresponding":true,"raw_author_name":"L. Behjat","raw_affiliation_strings":["Department of Electrical & Computer Engineering, University of Calgary, Calgary, AB, Canada"],"affiliations":[{"raw_affiliation_string":"Department of Electrical & Computer Engineering, University of Calgary, Calgary, AB, Canada","institution_ids":["https://openalex.org/I168635309"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5110267246","display_name":"Andy Chiang","orcid":null},"institutions":[{"id":"https://openalex.org/I168635309","display_name":"University of Calgary","ror":"https://ror.org/03yjb2x39","country_code":"CA","type":"education","lineage":["https://openalex.org/I168635309"]}],"countries":["CA"],"is_corresponding":false,"raw_author_name":"A. Chiang","raw_affiliation_strings":["Department of Electrical & Computer Engineering, University of Calgary, Calgary, AB, Canada"],"affiliations":[{"raw_affiliation_string":"Department of Electrical & Computer Engineering, University of Calgary, Calgary, AB, Canada","institution_ids":["https://openalex.org/I168635309"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":2,"corresponding_author_ids":["https://openalex.org/A5080379451"],"corresponding_institution_ids":["https://openalex.org/I168635309"],"apc_list":null,"apc_paid":null,"fwci":1.067,"has_fulltext":false,"cited_by_count":14,"citation_normalized_percentile":{"value":0.80328655,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":89,"max":95},"biblio":{"volume":null,"issue":null,"first_page":"6238","last_page":"6243"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T11522","display_name":"VLSI and FPGA Design Techniques","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T11522","display_name":"VLSI and FPGA Design Techniques","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11032","display_name":"VLSI and Analog Circuit Testing","score":0.9994999766349792,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":0.9988999962806702,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/router","display_name":"Router","score":0.7266720533370972},{"id":"https://openalex.org/keywords/integer-programming","display_name":"Integer programming","score":0.6912842988967896},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.684065580368042},{"id":"https://openalex.org/keywords/routing","display_name":"Routing (electronic design automation)","score":0.6708001494407654},{"id":"https://openalex.org/keywords/very-large-scale-integration","display_name":"Very-large-scale integration","score":0.6344340443611145},{"id":"https://openalex.org/keywords/mathematical-optimization","display_name":"Mathematical optimization","score":0.5959036946296692},{"id":"https://openalex.org/keywords/pruning","display_name":"Pruning","score":0.5523689985275269},{"id":"https://openalex.org/keywords/tree","display_name":"Tree (set theory)","score":0.5191851854324341},{"id":"https://openalex.org/keywords/minification","display_name":"Minification","score":0.49945807456970215},{"id":"https://openalex.org/keywords/linear-programming","display_name":"Linear programming","score":0.46641290187835693},{"id":"https://openalex.org/keywords/global-optimization","display_name":"Global optimization","score":0.4274233281612396},{"id":"https://openalex.org/keywords/parallel-computing","display_name":"Parallel computing","score":0.41928961873054504},{"id":"https://openalex.org/keywords/algorithm","display_name":"Algorithm","score":0.31853342056274414},{"id":"https://openalex.org/keywords/mathematics","display_name":"Mathematics","score":0.1983914077281952},{"id":"https://openalex.org/keywords/computer-network","display_name":"Computer network","score":0.08963707089424133},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.08727821707725525}],"concepts":[{"id":"https://openalex.org/C2775896111","wikidata":"https://www.wikidata.org/wiki/Q642560","display_name":"Router","level":2,"score":0.7266720533370972},{"id":"https://openalex.org/C56086750","wikidata":"https://www.wikidata.org/wiki/Q6042592","display_name":"Integer programming","level":2,"score":0.6912842988967896},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.684065580368042},{"id":"https://openalex.org/C74172769","wikidata":"https://www.wikidata.org/wiki/Q1446839","display_name":"Routing (electronic design automation)","level":2,"score":0.6708001494407654},{"id":"https://openalex.org/C14580979","wikidata":"https://www.wikidata.org/wiki/Q876049","display_name":"Very-large-scale integration","level":2,"score":0.6344340443611145},{"id":"https://openalex.org/C126255220","wikidata":"https://www.wikidata.org/wiki/Q141495","display_name":"Mathematical optimization","level":1,"score":0.5959036946296692},{"id":"https://openalex.org/C108010975","wikidata":"https://www.wikidata.org/wiki/Q500094","display_name":"Pruning","level":2,"score":0.5523689985275269},{"id":"https://openalex.org/C113174947","wikidata":"https://www.wikidata.org/wiki/Q2859736","display_name":"Tree (set theory)","level":2,"score":0.5191851854324341},{"id":"https://openalex.org/C147764199","wikidata":"https://www.wikidata.org/wiki/Q6865248","display_name":"Minification","level":2,"score":0.49945807456970215},{"id":"https://openalex.org/C41045048","wikidata":"https://www.wikidata.org/wiki/Q202843","display_name":"Linear programming","level":2,"score":0.46641290187835693},{"id":"https://openalex.org/C164752517","wikidata":"https://www.wikidata.org/wiki/Q5570875","display_name":"Global optimization","level":2,"score":0.4274233281612396},{"id":"https://openalex.org/C173608175","wikidata":"https://www.wikidata.org/wiki/Q232661","display_name":"Parallel computing","level":1,"score":0.41928961873054504},{"id":"https://openalex.org/C11413529","wikidata":"https://www.wikidata.org/wiki/Q8366","display_name":"Algorithm","level":1,"score":0.31853342056274414},{"id":"https://openalex.org/C33923547","wikidata":"https://www.wikidata.org/wiki/Q395","display_name":"Mathematics","level":0,"score":0.1983914077281952},{"id":"https://openalex.org/C31258907","wikidata":"https://www.wikidata.org/wiki/Q1301371","display_name":"Computer network","level":1,"score":0.08963707089424133},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.08727821707725525},{"id":"https://openalex.org/C134306372","wikidata":"https://www.wikidata.org/wiki/Q7754","display_name":"Mathematical analysis","level":1,"score":0.0},{"id":"https://openalex.org/C6557445","wikidata":"https://www.wikidata.org/wiki/Q173113","display_name":"Agronomy","level":1,"score":0.0},{"id":"https://openalex.org/C86803240","wikidata":"https://www.wikidata.org/wiki/Q420","display_name":"Biology","level":0,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/iscas.2005.1466066","is_oa":false,"landing_page_url":"https://doi.org/10.1109/iscas.2005.1466066","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2005 IEEE International Symposium on Circuits and Systems","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[],"awards":[],"funders":[{"id":"https://openalex.org/F4320334593","display_name":"Natural Sciences and Engineering Research Council of Canada","ror":"https://ror.org/01h531d29"}],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":20,"referenced_works":["https://openalex.org/W1522776502","https://openalex.org/W1987786682","https://openalex.org/W2006234018","https://openalex.org/W2018899219","https://openalex.org/W2028141257","https://openalex.org/W2036125948","https://openalex.org/W2069426496","https://openalex.org/W2098047532","https://openalex.org/W2126038273","https://openalex.org/W2157099685","https://openalex.org/W2159214117","https://openalex.org/W2162718901","https://openalex.org/W2168114925","https://openalex.org/W2168126808","https://openalex.org/W2168690316","https://openalex.org/W2611147814","https://openalex.org/W4205340856","https://openalex.org/W4300809515","https://openalex.org/W6631149369","https://openalex.org/W6684879859"],"related_works":["https://openalex.org/W2122026593","https://openalex.org/W2582203024","https://openalex.org/W1588358165","https://openalex.org/W4237683758","https://openalex.org/W2370711413","https://openalex.org/W2052038519","https://openalex.org/W2375932043","https://openalex.org/W2841075164","https://openalex.org/W1980506749","https://openalex.org/W4283025278"],"abstract_inverted_index":{"Global":[0],"routing":[1,96],"is":[2,88,148],"an":[3,99,167],"essential":[4],"part":[5],"of":[6,43,70,79,127,145,154,169,181],"VLSI":[7],"physical":[8],"design,":[9],"and":[10,158],"has":[11],"been":[12],"traditionally":[13],"solved":[14],"using":[15,59],"sequential":[16,22,45],"or":[17],"concurrent":[18,86],"methods.":[19],"In":[20,123],"the":[21,57,71,94,108,125,128,143,146,152,155,161,179,182],"techniques,":[23],"routes":[24],"are":[25,38,135],"generated":[26,130],"one":[27],"at":[28],"a":[29,33,67,76],"time":[30,174],"based":[31,84,141],"on":[32,85,142],"predetermined":[34],"ordering.":[35],"These":[36,63],"methods":[37,64],"very":[39],"fast,":[40],"but":[41,74],"because":[42],"their":[44],"nature":[46],"can":[47,65],"result":[48],"in":[49,172,178],"sub-optimal":[50],"solutions.":[51],"Concurrent":[52],"techniques":[53,87],"attempt":[54],"to":[55,118,150],"solve":[56],"problem":[58,97],"global":[60,68,82,95,133],"optimization":[61],"techniques.":[62],"provide":[66],"view":[69],"circuit's":[72],"routing,":[73],"take":[75],"considerable":[77],"amount":[78],"time.":[80,163],"A":[81,137],"router":[83,134],"presented.":[89],"The":[90,164],"proposed":[91],"technique":[92],"formulates":[93],"as":[98],"integer":[100],"linear":[101],"programming":[102],"(ILP)":[103],"problem.":[104],"This":[105],"model":[106,113],"combines":[107],"traditional":[109],"wire":[110],"length":[111],"minimization":[112,117],"with":[114],"channel":[115],"capacity":[116],"obtain":[119],"more":[120],"accurate":[121],"routings.":[122],"addition,":[124],"characteristics":[126,144],"trees":[129],"by":[131],"our":[132],"investigated.":[136],"tree":[138],"pruning":[139],"technique,":[140],"trees,":[147],"developed":[149],"reduce":[151,160],"size":[153],"ILP":[156],"problem,":[157],"consequently":[159],"solution":[162],"results":[165],"show":[166],"average":[168],"58%":[170],"improvement":[171],"solving":[173],"without":[175],"any":[176],"loss":[177],"quality":[180],"results.":[183]},"counts_by_year":[{"year":2025,"cited_by_count":1},{"year":2020,"cited_by_count":1},{"year":2018,"cited_by_count":1},{"year":2014,"cited_by_count":1},{"year":2013,"cited_by_count":1},{"year":2012,"cited_by_count":1}],"updated_date":"2025-11-06T03:46:38.306776","created_date":"2025-10-10T00:00:00"}
