{"id":"https://openalex.org/W2107449576","doi":"https://doi.org/10.1109/iscas.2005.1465989","title":"System LSI Design with C-based Behavioral Synthesis and Verification","display_name":"System LSI Design with C-based Behavioral Synthesis and Verification","publication_year":2005,"publication_date":"2005-07-27","ids":{"openalex":"https://openalex.org/W2107449576","doi":"https://doi.org/10.1109/iscas.2005.1465989","mag":"2107449576"},"language":"en","primary_location":{"id":"doi:10.1109/iscas.2005.1465989","is_oa":false,"landing_page_url":"https://doi.org/10.1109/iscas.2005.1465989","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2005 IEEE International Symposium on Circuits and Systems","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5085369368","display_name":"Katsunori Wakabayashi","orcid":"https://orcid.org/0000-0002-9147-9939"},"institutions":[{"id":"https://openalex.org/I118347220","display_name":"NEC (Japan)","ror":"https://ror.org/04jndar25","country_code":"JP","type":"company","lineage":["https://openalex.org/I118347220"]}],"countries":["JP"],"is_corresponding":true,"raw_author_name":"K. Wakabayashi","raw_affiliation_strings":["System Devices Research Laboratories, NEC Corporation Limited, Kawasaki, Japan","Syst. Devices Res. Labs., NEC Corp., Kawasaki, Japan"],"affiliations":[{"raw_affiliation_string":"System Devices Research Laboratories, NEC Corporation Limited, Kawasaki, Japan","institution_ids":["https://openalex.org/I118347220"]},{"raw_affiliation_string":"Syst. Devices Res. Labs., NEC Corp., Kawasaki, Japan","institution_ids":["https://openalex.org/I118347220"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":1,"corresponding_author_ids":["https://openalex.org/A5085369368"],"corresponding_institution_ids":["https://openalex.org/I118347220"],"apc_list":null,"apc_paid":null,"fwci":0.0,"has_fulltext":false,"cited_by_count":1,"citation_normalized_percentile":{"value":0.16911139,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":89,"max":93},"biblio":{"volume":"e85 a","issue":null,"first_page":"5930","last_page":"5933"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10904","display_name":"Embedded Systems Design Techniques","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10904","display_name":"Embedded Systems Design Techniques","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11522","display_name":"VLSI and FPGA Design Techniques","score":0.9954000115394592,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11032","display_name":"VLSI and Analog Circuit Testing","score":0.9950000047683716,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.7145938277244568},{"id":"https://openalex.org/keywords/behavioral-modeling","display_name":"Behavioral modeling","score":0.6010109782218933},{"id":"https://openalex.org/keywords/design-flow","display_name":"Design flow","score":0.5778494477272034},{"id":"https://openalex.org/keywords/computer-architecture","display_name":"Computer architecture","score":0.5340349674224854},{"id":"https://openalex.org/keywords/hardware-description-language","display_name":"Hardware description language","score":0.46349239349365234},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.43513017892837524},{"id":"https://openalex.org/keywords/logic-synthesis","display_name":"Logic synthesis","score":0.42703568935394287},{"id":"https://openalex.org/keywords/high-level-synthesis","display_name":"High-level synthesis","score":0.4219357967376709},{"id":"https://openalex.org/keywords/programming-language","display_name":"Programming language","score":0.3366941213607788},{"id":"https://openalex.org/keywords/field-programmable-gate-array","display_name":"Field-programmable gate array","score":0.23928353190422058},{"id":"https://openalex.org/keywords/logic-gate","display_name":"Logic gate","score":0.21729731559753418},{"id":"https://openalex.org/keywords/artificial-intelligence","display_name":"Artificial intelligence","score":0.10137489438056946},{"id":"https://openalex.org/keywords/algorithm","display_name":"Algorithm","score":0.07892140746116638}],"concepts":[{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.7145938277244568},{"id":"https://openalex.org/C78639753","wikidata":"https://www.wikidata.org/wiki/Q3318160","display_name":"Behavioral modeling","level":2,"score":0.6010109782218933},{"id":"https://openalex.org/C37135326","wikidata":"https://www.wikidata.org/wiki/Q931942","display_name":"Design flow","level":2,"score":0.5778494477272034},{"id":"https://openalex.org/C118524514","wikidata":"https://www.wikidata.org/wiki/Q173212","display_name":"Computer architecture","level":1,"score":0.5340349674224854},{"id":"https://openalex.org/C42143788","wikidata":"https://www.wikidata.org/wiki/Q173341","display_name":"Hardware description language","level":3,"score":0.46349239349365234},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.43513017892837524},{"id":"https://openalex.org/C157922185","wikidata":"https://www.wikidata.org/wiki/Q173198","display_name":"Logic synthesis","level":3,"score":0.42703568935394287},{"id":"https://openalex.org/C58013763","wikidata":"https://www.wikidata.org/wiki/Q5754574","display_name":"High-level synthesis","level":3,"score":0.4219357967376709},{"id":"https://openalex.org/C199360897","wikidata":"https://www.wikidata.org/wiki/Q9143","display_name":"Programming language","level":1,"score":0.3366941213607788},{"id":"https://openalex.org/C42935608","wikidata":"https://www.wikidata.org/wiki/Q190411","display_name":"Field-programmable gate array","level":2,"score":0.23928353190422058},{"id":"https://openalex.org/C131017901","wikidata":"https://www.wikidata.org/wiki/Q170451","display_name":"Logic gate","level":2,"score":0.21729731559753418},{"id":"https://openalex.org/C154945302","wikidata":"https://www.wikidata.org/wiki/Q11660","display_name":"Artificial intelligence","level":1,"score":0.10137489438056946},{"id":"https://openalex.org/C11413529","wikidata":"https://www.wikidata.org/wiki/Q8366","display_name":"Algorithm","level":1,"score":0.07892140746116638}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/iscas.2005.1465989","is_oa":false,"landing_page_url":"https://doi.org/10.1109/iscas.2005.1465989","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2005 IEEE International Symposium on Circuits and Systems","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[],"awards":[],"funders":[],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":4,"referenced_works":["https://openalex.org/W598232747","https://openalex.org/W2130513448","https://openalex.org/W2141710608","https://openalex.org/W6617973945"],"related_works":["https://openalex.org/W3002976045","https://openalex.org/W2269990635","https://openalex.org/W4247178515","https://openalex.org/W2543290882","https://openalex.org/W2097236935","https://openalex.org/W1491192879","https://openalex.org/W2295153704","https://openalex.org/W3013057549","https://openalex.org/W1980040075","https://openalex.org/W1490270176"],"abstract_inverted_index":{"The":[0,14,31],"paper":[1],"presents":[2],"the":[3],"effects":[4],"of":[5,33],"system":[6,27],"LSI":[7,28],"design":[8],"with":[9],"C":[10],"language-based":[11],"behavioral":[12,34],"synthesis.":[13],"proposed":[15],"C-based":[16],"tool":[17],"flow":[18],"and":[19,23,37],"how":[20],"to":[21],"synthesize":[22],"verify":[24],"an":[25],"entire":[26],"are":[29,40],"explained.":[30],"merits":[32],"synthesizable":[35],"modules":[36],"configurable":[38],"processors":[39],"then":[41],"discussed.":[42]},"counts_by_year":[{"year":2021,"cited_by_count":1}],"updated_date":"2025-11-06T03:46:38.306776","created_date":"2025-10-10T00:00:00"}