{"id":"https://openalex.org/W2142074420","doi":"https://doi.org/10.1109/iscas.2003.1206173","title":"An efficient reduced-order interconnect macromodel for time-domain simulation","display_name":"An efficient reduced-order interconnect macromodel for time-domain simulation","publication_year":2003,"publication_date":"2003-11-04","ids":{"openalex":"https://openalex.org/W2142074420","doi":"https://doi.org/10.1109/iscas.2003.1206173","mag":"2142074420"},"language":"en","primary_location":{"id":"doi:10.1109/iscas.2003.1206173","is_oa":false,"landing_page_url":"https://doi.org/10.1109/iscas.2003.1206173","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Proceedings of the 2003 International Symposium on Circuits and Systems, 2003. ISCAS '03.","raw_type":"proceedings-article"},"type":"conference-paper","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5076683470","display_name":"T. Palenius","orcid":null},"institutions":[],"countries":[],"is_corresponding":false,"raw_author_name":"T. Palenius","raw_affiliation_strings":["Department of Electrical and Communications Engineering, Circuit Theory Laboratory, Helsinki University of Technology, Finland","Dept. of Electr. & Commun. Eng., Helsinki Univ. of Technol., Finland"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Department of Electrical and Communications Engineering, Circuit Theory Laboratory, Helsinki University of Technology, Finland","institution_ids":[]},{"raw_affiliation_string":"Dept. of Electr. & Commun. Eng., Helsinki Univ. of Technol., Finland","institution_ids":[]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5057856783","display_name":"Janne Roos","orcid":null},"institutions":[],"countries":[],"is_corresponding":false,"raw_author_name":"J. Roos","raw_affiliation_strings":["Department of Electrical and Communications Engineering, Circuit Theory Laboratory, Helsinki University of Technology, Finland","Dept. of Electr. & Commun. Eng., Helsinki Univ. of Technol., Finland"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Department of Electrical and Communications Engineering, Circuit Theory Laboratory, Helsinki University of Technology, Finland","institution_ids":[]},{"raw_affiliation_string":"Dept. of Electr. & Commun. Eng., Helsinki Univ. of Technol., Finland","institution_ids":[]}]}],"institutions":[],"countries_distinct_count":0,"institutions_distinct_count":0,"corresponding_author_ids":[],"corresponding_institution_ids":[],"apc_list":null,"apc_paid":null,"fwci":0.5151,"has_fulltext":false,"cited_by_count":2,"citation_normalized_percentile":{"value":0.71686747,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":null,"biblio":{"volume":"4","issue":null,"first_page":"IV","last_page":"628"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T11206","display_name":"Model Reduction and Neural Networks","score":0.9983000159263611,"subfield":{"id":"https://openalex.org/subfields/3109","display_name":"Statistical and Nonlinear Physics"},"field":{"id":"https://openalex.org/fields/31","display_name":"Physics and Astronomy"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T11206","display_name":"Model Reduction and Neural Networks","score":0.9983000159263611,"subfield":{"id":"https://openalex.org/subfields/3109","display_name":"Statistical and Nonlinear Physics"},"field":{"id":"https://openalex.org/fields/31","display_name":"Physics and Astronomy"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T12810","display_name":"Real-time simulation and control systems","score":0.9837999939918518,"subfield":{"id":"https://openalex.org/subfields/2207","display_name":"Control and Systems Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":0.9782000184059143,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/rlc-circuit","display_name":"RLC circuit","score":0.8334797620773315},{"id":"https://openalex.org/keywords/interfacing","display_name":"Interfacing","score":0.8046557903289795},{"id":"https://openalex.org/keywords/interconnection","display_name":"Interconnection","score":0.6613699197769165},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.6541310548782349},{"id":"https://openalex.org/keywords/frequency-domain","display_name":"Frequency domain","score":0.6098137497901917},{"id":"https://openalex.org/keywords/time-domain","display_name":"Time domain","score":0.5870687961578369},{"id":"https://openalex.org/keywords/electronic-engineering","display_name":"Electronic engineering","score":0.5867180228233337},{"id":"https://openalex.org/keywords/very-large-scale-integration","display_name":"Very-large-scale integration","score":0.5813838243484497},{"id":"https://openalex.org/keywords/domain","display_name":"Domain (mathematical analysis)","score":0.47964149713516235},{"id":"https://openalex.org/keywords/model-order-reduction","display_name":"Model order reduction","score":0.47757914662361145},{"id":"https://openalex.org/keywords/reduction","display_name":"Reduction (mathematics)","score":0.45345258712768555},{"id":"https://openalex.org/keywords/electronic-circuit","display_name":"Electronic circuit","score":0.41500186920166016},{"id":"https://openalex.org/keywords/algorithm","display_name":"Algorithm","score":0.20838934183120728},{"id":"https://openalex.org/keywords/telecommunications","display_name":"Telecommunications","score":0.20721140503883362},{"id":"https://openalex.org/keywords/electrical-engineering","display_name":"Electrical engineering","score":0.20173978805541992},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.16205599904060364},{"id":"https://openalex.org/keywords/mathematics","display_name":"Mathematics","score":0.11473220586776733},{"id":"https://openalex.org/keywords/computer-hardware","display_name":"Computer hardware","score":0.10676836967468262},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.10659235715866089},{"id":"https://openalex.org/keywords/capacitor","display_name":"Capacitor","score":0.0842018723487854},{"id":"https://openalex.org/keywords/voltage","display_name":"Voltage","score":0.07282957434654236}],"concepts":[{"id":"https://openalex.org/C89880566","wikidata":"https://www.wikidata.org/wiki/Q323477","display_name":"RLC circuit","level":4,"score":0.8334797620773315},{"id":"https://openalex.org/C2776303644","wikidata":"https://www.wikidata.org/wiki/Q1020499","display_name":"Interfacing","level":2,"score":0.8046557903289795},{"id":"https://openalex.org/C123745756","wikidata":"https://www.wikidata.org/wiki/Q1665949","display_name":"Interconnection","level":2,"score":0.6613699197769165},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.6541310548782349},{"id":"https://openalex.org/C19118579","wikidata":"https://www.wikidata.org/wiki/Q786423","display_name":"Frequency domain","level":2,"score":0.6098137497901917},{"id":"https://openalex.org/C103824480","wikidata":"https://www.wikidata.org/wiki/Q185889","display_name":"Time domain","level":2,"score":0.5870687961578369},{"id":"https://openalex.org/C24326235","wikidata":"https://www.wikidata.org/wiki/Q126095","display_name":"Electronic engineering","level":1,"score":0.5867180228233337},{"id":"https://openalex.org/C14580979","wikidata":"https://www.wikidata.org/wiki/Q876049","display_name":"Very-large-scale integration","level":2,"score":0.5813838243484497},{"id":"https://openalex.org/C36503486","wikidata":"https://www.wikidata.org/wiki/Q11235244","display_name":"Domain (mathematical analysis)","level":2,"score":0.47964149713516235},{"id":"https://openalex.org/C2779277453","wikidata":"https://www.wikidata.org/wiki/Q12202921","display_name":"Model order reduction","level":3,"score":0.47757914662361145},{"id":"https://openalex.org/C111335779","wikidata":"https://www.wikidata.org/wiki/Q3454686","display_name":"Reduction (mathematics)","level":2,"score":0.45345258712768555},{"id":"https://openalex.org/C134146338","wikidata":"https://www.wikidata.org/wiki/Q1815901","display_name":"Electronic circuit","level":2,"score":0.41500186920166016},{"id":"https://openalex.org/C11413529","wikidata":"https://www.wikidata.org/wiki/Q8366","display_name":"Algorithm","level":1,"score":0.20838934183120728},{"id":"https://openalex.org/C76155785","wikidata":"https://www.wikidata.org/wiki/Q418","display_name":"Telecommunications","level":1,"score":0.20721140503883362},{"id":"https://openalex.org/C119599485","wikidata":"https://www.wikidata.org/wiki/Q43035","display_name":"Electrical engineering","level":1,"score":0.20173978805541992},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.16205599904060364},{"id":"https://openalex.org/C33923547","wikidata":"https://www.wikidata.org/wiki/Q395","display_name":"Mathematics","level":0,"score":0.11473220586776733},{"id":"https://openalex.org/C9390403","wikidata":"https://www.wikidata.org/wiki/Q3966","display_name":"Computer hardware","level":1,"score":0.10676836967468262},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.10659235715866089},{"id":"https://openalex.org/C52192207","wikidata":"https://www.wikidata.org/wiki/Q5322","display_name":"Capacitor","level":3,"score":0.0842018723487854},{"id":"https://openalex.org/C165801399","wikidata":"https://www.wikidata.org/wiki/Q25428","display_name":"Voltage","level":2,"score":0.07282957434654236},{"id":"https://openalex.org/C2524010","wikidata":"https://www.wikidata.org/wiki/Q8087","display_name":"Geometry","level":1,"score":0.0},{"id":"https://openalex.org/C57493831","wikidata":"https://www.wikidata.org/wiki/Q3134666","display_name":"Projection (relational algebra)","level":2,"score":0.0},{"id":"https://openalex.org/C134306372","wikidata":"https://www.wikidata.org/wiki/Q7754","display_name":"Mathematical analysis","level":1,"score":0.0},{"id":"https://openalex.org/C31972630","wikidata":"https://www.wikidata.org/wiki/Q844240","display_name":"Computer vision","level":1,"score":0.0}],"mesh":[],"locations_count":2,"locations":[{"id":"doi:10.1109/iscas.2003.1206173","is_oa":false,"landing_page_url":"https://doi.org/10.1109/iscas.2003.1206173","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Proceedings of the 2003 International Symposium on Circuits and Systems, 2003. ISCAS '03.","raw_type":"proceedings-article"},{"id":"pmh:oai:CiteSeerX.psu:10.1.1.946.763","is_oa":false,"landing_page_url":"http://citeseerx.ist.psu.edu/viewdoc/summary?doi=10.1.1.946.763","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"submittedVersion","is_accepted":false,"is_published":false,"raw_source_name":"http://est3.lmn.pub.ro/communication/Matsumoto/JanneRoos_met_sinteza.pdf","raw_type":"text"}],"best_oa_location":null,"sustainable_development_goals":[{"score":0.6299999952316284,"id":"https://metadata.un.org/sdg/7","display_name":"Affordable and clean energy"}],"awards":[],"funders":[],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":7,"referenced_works":["https://openalex.org/W1934566074","https://openalex.org/W2089443862","https://openalex.org/W2112149126","https://openalex.org/W2122608783","https://openalex.org/W2156072724","https://openalex.org/W3145363696","https://openalex.org/W4285719527"],"related_works":["https://openalex.org/W2081032080","https://openalex.org/W2134733504","https://openalex.org/W2374241634","https://openalex.org/W2144460576","https://openalex.org/W2101451133","https://openalex.org/W2040376333","https://openalex.org/W2096076987","https://openalex.org/W2245072813","https://openalex.org/W2067716188","https://openalex.org/W2060336335"],"abstract_inverted_index":{"As":[0],"signal":[1],"speeds":[2],"grow":[3],"and":[4],"feature":[5],"sizes":[6],"shrink":[7],"in":[8],"digital":[9],"VLSI":[10],"circuits,":[11],"there":[12],"is":[13],"an":[14,54],"increasing":[15],"need":[16],"to":[17],"correctly":[18],"model":[19],"the":[20,25,28,42,63,67],"interconnects":[21],"between":[22],"transistors.":[23],"Since":[24],"size":[26],"of":[27,66],"resulting":[29],"RLC-interconnect":[30],"network":[31],"can":[32],"be":[33],"huge,":[34],"model-reduction":[35],"algorithms":[36],"have":[37],"been":[38],"developed":[39],"for":[40,57],"replacing":[41],"RLC":[43],"networks":[44],"with":[45,62],"reduced-order":[46],"frequency-domain":[47,60],"models.":[48],"In":[49],"this":[50],"paper,":[51],"we":[52],"present":[53],"efficient":[55],"method":[56],"interfacing":[58],"these":[59],"representations":[61],"time-domain":[64],"simulation":[65],"original":[68],"nonlinear":[69],"circuit.":[70]},"counts_by_year":[],"updated_date":"2026-08-26T07:47:46.906454","created_date":"2025-10-10T00:00:00"}
