{"id":"https://openalex.org/W2157091107","doi":"https://doi.org/10.1109/iscas.2002.1010170","title":"Implementation oriented theory design issues on the DTCNN template generation","display_name":"Implementation oriented theory design issues on the DTCNN template generation","publication_year":2003,"publication_date":"2003-06-25","ids":{"openalex":"https://openalex.org/W2157091107","doi":"https://doi.org/10.1109/iscas.2002.1010170","mag":"2157091107"},"language":"en","primary_location":{"id":"doi:10.1109/iscas.2002.1010170","is_oa":false,"landing_page_url":"https://doi.org/10.1109/iscas.2002.1010170","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2002 IEEE International Symposium on Circuits and Systems. Proceedings (Cat. No.02CH37353)","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5077550469","display_name":"V.M. Brea","orcid":"https://orcid.org/0000-0003-0078-0425"},"institutions":[{"id":"https://openalex.org/I200284239","display_name":"Universidade de Santiago de Compostela","ror":"https://ror.org/030eybx10","country_code":"ES","type":"education","lineage":["https://openalex.org/I200284239"]}],"countries":["ES"],"is_corresponding":false,"raw_author_name":"V.M. Brea","raw_affiliation_strings":["Department of Electronics and Computer Science, University of Santiago de Compostela, Santiago de Compostela, Spain"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Department of Electronics and Computer Science, University of Santiago de Compostela, Santiago de Compostela, Spain","institution_ids":["https://openalex.org/I200284239"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5083070796","display_name":"D.L. Vilari\u00f1o","orcid":"https://orcid.org/0000-0002-4405-2924"},"institutions":[{"id":"https://openalex.org/I200284239","display_name":"Universidade de Santiago de Compostela","ror":"https://ror.org/030eybx10","country_code":"ES","type":"education","lineage":["https://openalex.org/I200284239"]}],"countries":["ES"],"is_corresponding":false,"raw_author_name":"D.L. Vilarino","raw_affiliation_strings":["Department of Electronics and Computer Science, University of Santiago de Compostela, Santiago de Compostela, Spain"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Department of Electronics and Computer Science, University of Santiago de Compostela, Santiago de Compostela, Spain","institution_ids":["https://openalex.org/I200284239"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5038944203","display_name":"A. Paasio","orcid":"https://orcid.org/0000-0003-2543-7391"},"institutions":[],"countries":[],"is_corresponding":false,"raw_author_name":"A. Paasio","raw_affiliation_strings":["Electronic Circuit Design Laboratory, Helsinki University of Technology, Finland"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Electronic Circuit Design Laboratory, Helsinki University of Technology, Finland","institution_ids":[]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5041970396","display_name":"D. Cabello","orcid":"https://orcid.org/0000-0002-4859-2899"},"institutions":[{"id":"https://openalex.org/I200284239","display_name":"Universidade de Santiago de Compostela","ror":"https://ror.org/030eybx10","country_code":"ES","type":"education","lineage":["https://openalex.org/I200284239"]}],"countries":["ES"],"is_corresponding":false,"raw_author_name":"D. Cabello","raw_affiliation_strings":["Department of Electronics and Computer Science, University of Santiago de Compostela, Santiago de Compostela, Spain"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Department of Electronics and Computer Science, University of Santiago de Compostela, Santiago de Compostela, Spain","institution_ids":["https://openalex.org/I200284239"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":4,"corresponding_author_ids":[],"corresponding_institution_ids":[],"apc_list":null,"apc_paid":null,"fwci":0.0,"has_fulltext":false,"cited_by_count":0,"citation_normalized_percentile":{"value":0.21721728,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":null,"biblio":{"volume":"3","issue":null,"first_page":"III","last_page":"101"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10502","display_name":"Advanced Memory and Neural Computing","score":0.9975000023841858,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10502","display_name":"Advanced Memory and Neural Computing","score":0.9975000023841858,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T12808","display_name":"Ferroelectric and Negative Capacitance Devices","score":0.9948999881744385,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T12611","display_name":"Neural Networks and Reservoir Computing","score":0.9933000206947327,"subfield":{"id":"https://openalex.org/subfields/1702","display_name":"Artificial Intelligence"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.6766636967658997},{"id":"https://openalex.org/keywords/process","display_name":"Process (computing)","score":0.5850497484207153},{"id":"https://openalex.org/keywords/chip","display_name":"Chip","score":0.5688303112983704},{"id":"https://openalex.org/keywords/pixel","display_name":"Pixel","score":0.5678319931030273},{"id":"https://openalex.org/keywords/cmos","display_name":"CMOS","score":0.5526394248008728},{"id":"https://openalex.org/keywords/algorithm-design","display_name":"Algorithm design","score":0.5110567808151245},{"id":"https://openalex.org/keywords/system-on-a-chip","display_name":"System on a chip","score":0.46476539969444275},{"id":"https://openalex.org/keywords/integrated-circuit-design","display_name":"Integrated circuit design","score":0.4552324414253235},{"id":"https://openalex.org/keywords/algorithm","display_name":"Algorithm","score":0.39999887347221375},{"id":"https://openalex.org/keywords/computer-engineering","display_name":"Computer engineering","score":0.3800012469291687},{"id":"https://openalex.org/keywords/electronic-engineering","display_name":"Electronic engineering","score":0.31147390604019165},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.24689245223999023},{"id":"https://openalex.org/keywords/artificial-intelligence","display_name":"Artificial intelligence","score":0.2086051106452942},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.1724485158920288},{"id":"https://openalex.org/keywords/programming-language","display_name":"Programming language","score":0.09717810153961182},{"id":"https://openalex.org/keywords/telecommunications","display_name":"Telecommunications","score":0.09293371438980103}],"concepts":[{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.6766636967658997},{"id":"https://openalex.org/C98045186","wikidata":"https://www.wikidata.org/wiki/Q205663","display_name":"Process (computing)","level":2,"score":0.5850497484207153},{"id":"https://openalex.org/C165005293","wikidata":"https://www.wikidata.org/wiki/Q1074500","display_name":"Chip","level":2,"score":0.5688303112983704},{"id":"https://openalex.org/C160633673","wikidata":"https://www.wikidata.org/wiki/Q355198","display_name":"Pixel","level":2,"score":0.5678319931030273},{"id":"https://openalex.org/C46362747","wikidata":"https://www.wikidata.org/wiki/Q173431","display_name":"CMOS","level":2,"score":0.5526394248008728},{"id":"https://openalex.org/C106516650","wikidata":"https://www.wikidata.org/wiki/Q8366","display_name":"Algorithm design","level":2,"score":0.5110567808151245},{"id":"https://openalex.org/C118021083","wikidata":"https://www.wikidata.org/wiki/Q610398","display_name":"System on a chip","level":2,"score":0.46476539969444275},{"id":"https://openalex.org/C74524168","wikidata":"https://www.wikidata.org/wiki/Q1074539","display_name":"Integrated circuit design","level":2,"score":0.4552324414253235},{"id":"https://openalex.org/C11413529","wikidata":"https://www.wikidata.org/wiki/Q8366","display_name":"Algorithm","level":1,"score":0.39999887347221375},{"id":"https://openalex.org/C113775141","wikidata":"https://www.wikidata.org/wiki/Q428691","display_name":"Computer engineering","level":1,"score":0.3800012469291687},{"id":"https://openalex.org/C24326235","wikidata":"https://www.wikidata.org/wiki/Q126095","display_name":"Electronic engineering","level":1,"score":0.31147390604019165},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.24689245223999023},{"id":"https://openalex.org/C154945302","wikidata":"https://www.wikidata.org/wiki/Q11660","display_name":"Artificial intelligence","level":1,"score":0.2086051106452942},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.1724485158920288},{"id":"https://openalex.org/C199360897","wikidata":"https://www.wikidata.org/wiki/Q9143","display_name":"Programming language","level":1,"score":0.09717810153961182},{"id":"https://openalex.org/C76155785","wikidata":"https://www.wikidata.org/wiki/Q418","display_name":"Telecommunications","level":1,"score":0.09293371438980103}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/iscas.2002.1010170","is_oa":false,"landing_page_url":"https://doi.org/10.1109/iscas.2002.1010170","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2002 IEEE International Symposium on Circuits and Systems. Proceedings (Cat. No.02CH37353)","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[],"awards":[],"funders":[],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":12,"referenced_works":["https://openalex.org/W200398567","https://openalex.org/W571960815","https://openalex.org/W1037205816","https://openalex.org/W1479718318","https://openalex.org/W2036831172","https://openalex.org/W2128884888","https://openalex.org/W2140608165","https://openalex.org/W2140823559","https://openalex.org/W2142449791","https://openalex.org/W2149890110","https://openalex.org/W2429227013","https://openalex.org/W6717893161"],"related_works":["https://openalex.org/W2065289416","https://openalex.org/W2017236304","https://openalex.org/W2038859986","https://openalex.org/W2104315811","https://openalex.org/W2142217172","https://openalex.org/W1982273910","https://openalex.org/W1929041301","https://openalex.org/W4230312832","https://openalex.org/W2115579119","https://openalex.org/W2110366946"],"abstract_inverted_index":{"This":[0],"paper":[1],"collects":[2],"all":[3],"the":[4,9,14,38,68],"hardware":[5],"constraints":[6],"considered":[7],"during":[8],"system-level":[10],"design":[11],"phase":[12],"of":[13,47],"so-called":[15],"DTCNN":[16,59],"pixel-level":[17],"snake":[18],"algorithm":[19],"(PLS-algorithm).":[20],"These":[21],"constraints,":[22],"although":[23],"focused":[24],"on":[25],"a":[26,56],"particular":[27],"algorithm,":[28],"can":[29],"be":[30],"taken":[31],"as":[32],"general":[33],"guidelines":[34],"aimed":[35],"to":[36],"achieve":[37],"lowest":[39],"coefficient":[40],"circuit":[41],"area":[42],"in":[43,67],"DTCNN.":[44],"The":[45],"validity":[46],"this":[48],"approach":[49],"is":[50,64],"illustrated":[51],"with":[52],"some":[53],"data":[54],"about":[55],"9/spl":[57],"times/9":[58],"PLS-algorithm":[60],"chip,":[61],"which":[62],"nowadays":[63],"being":[65],"made":[66],"0.25":[69],"/spl":[70],"mu/m":[71],"CMOS":[72],"technology":[73],"process":[74],"provided":[75],"by":[76],"THOMSON.":[77]},"counts_by_year":[],"updated_date":"2026-06-11T09:08:48.828518","created_date":"2025-10-10T00:00:00"}
