{"id":"https://openalex.org/W1554898868","doi":"https://doi.org/10.1109/iscas.1994.408778","title":"Worst case design of digital integrated circuits","display_name":"Worst case design of digital integrated circuits","publication_year":1994,"publication_date":"1994-01-01","ids":{"openalex":"https://openalex.org/W1554898868","doi":"https://doi.org/10.1109/iscas.1994.408778","mag":"1554898868"},"language":"en","primary_location":{"id":"doi:10.1109/iscas.1994.408778","is_oa":false,"landing_page_url":"https://doi.org/10.1109/iscas.1994.408778","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"1994 IEEE International Symposium on Circuits and Systems (ISCAS)","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5088150052","display_name":"J.C. Zhang","orcid":null},"institutions":[],"countries":[],"is_corresponding":true,"raw_author_name":"J.C. Zhang","raw_affiliation_strings":["Dept. of Res. & Dev., Western Atlas Inc., Houston, TX, USA"],"affiliations":[{"raw_affiliation_string":"Dept. of Res. & Dev., Western Atlas Inc., Houston, TX, USA","institution_ids":[]}]}],"institutions":[],"countries_distinct_count":0,"institutions_distinct_count":1,"corresponding_author_ids":["https://openalex.org/A5088150052"],"corresponding_institution_ids":[],"apc_list":null,"apc_paid":null,"fwci":0.0,"has_fulltext":false,"cited_by_count":4,"citation_normalized_percentile":{"value":0.04908287,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":90,"max":94},"biblio":{"volume":null,"issue":null,"first_page":"153","last_page":"156 vol.1"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":0.989300012588501,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":0.989300012588501,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10323","display_name":"Analog and Mixed-Signal Circuit Design","score":0.9811999797821045,"subfield":{"id":"https://openalex.org/subfields/2204","display_name":"Biomedical Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11522","display_name":"VLSI and FPGA Design Techniques","score":0.968999981880188,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/cmos","display_name":"CMOS","score":0.7216351628303528},{"id":"https://openalex.org/keywords/sigma","display_name":"Sigma","score":0.6249996423721313},{"id":"https://openalex.org/keywords/minification","display_name":"Minification","score":0.6209776401519775},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.5524911284446716},{"id":"https://openalex.org/keywords/integrated-circuit","display_name":"Integrated circuit","score":0.540975034236908},{"id":"https://openalex.org/keywords/integrated-circuit-design","display_name":"Integrated circuit design","score":0.5245057344436646},{"id":"https://openalex.org/keywords/transistor","display_name":"Transistor","score":0.5238105058670044},{"id":"https://openalex.org/keywords/reduction","display_name":"Reduction (mathematics)","score":0.5130459070205688},{"id":"https://openalex.org/keywords/digital-electronics","display_name":"Digital electronics","score":0.5033857226371765},{"id":"https://openalex.org/keywords/electronic-engineering","display_name":"Electronic engineering","score":0.4574526846408844},{"id":"https://openalex.org/keywords/measure","display_name":"Measure (data warehouse)","score":0.4568593502044678},{"id":"https://openalex.org/keywords/electronic-circuit","display_name":"Electronic circuit","score":0.45609772205352783},{"id":"https://openalex.org/keywords/mixed-signal-integrated-circuit","display_name":"Mixed-signal integrated circuit","score":0.44501248002052307},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.22744473814964294},{"id":"https://openalex.org/keywords/mathematics","display_name":"Mathematics","score":0.21435365080833435},{"id":"https://openalex.org/keywords/electrical-engineering","display_name":"Electrical engineering","score":0.2047133445739746},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.14219895005226135},{"id":"https://openalex.org/keywords/data-mining","display_name":"Data mining","score":0.13163694739341736},{"id":"https://openalex.org/keywords/programming-language","display_name":"Programming language","score":0.07685104012489319},{"id":"https://openalex.org/keywords/physics","display_name":"Physics","score":0.06416794657707214}],"concepts":[{"id":"https://openalex.org/C46362747","wikidata":"https://www.wikidata.org/wiki/Q173431","display_name":"CMOS","level":2,"score":0.7216351628303528},{"id":"https://openalex.org/C2778049214","wikidata":"https://www.wikidata.org/wiki/Q7512234","display_name":"Sigma","level":2,"score":0.6249996423721313},{"id":"https://openalex.org/C147764199","wikidata":"https://www.wikidata.org/wiki/Q6865248","display_name":"Minification","level":2,"score":0.6209776401519775},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.5524911284446716},{"id":"https://openalex.org/C530198007","wikidata":"https://www.wikidata.org/wiki/Q80831","display_name":"Integrated circuit","level":2,"score":0.540975034236908},{"id":"https://openalex.org/C74524168","wikidata":"https://www.wikidata.org/wiki/Q1074539","display_name":"Integrated circuit design","level":2,"score":0.5245057344436646},{"id":"https://openalex.org/C172385210","wikidata":"https://www.wikidata.org/wiki/Q5339","display_name":"Transistor","level":3,"score":0.5238105058670044},{"id":"https://openalex.org/C111335779","wikidata":"https://www.wikidata.org/wiki/Q3454686","display_name":"Reduction (mathematics)","level":2,"score":0.5130459070205688},{"id":"https://openalex.org/C81843906","wikidata":"https://www.wikidata.org/wiki/Q173156","display_name":"Digital electronics","level":3,"score":0.5033857226371765},{"id":"https://openalex.org/C24326235","wikidata":"https://www.wikidata.org/wiki/Q126095","display_name":"Electronic engineering","level":1,"score":0.4574526846408844},{"id":"https://openalex.org/C2780009758","wikidata":"https://www.wikidata.org/wiki/Q6804172","display_name":"Measure (data warehouse)","level":2,"score":0.4568593502044678},{"id":"https://openalex.org/C134146338","wikidata":"https://www.wikidata.org/wiki/Q1815901","display_name":"Electronic circuit","level":2,"score":0.45609772205352783},{"id":"https://openalex.org/C62907940","wikidata":"https://www.wikidata.org/wiki/Q1541329","display_name":"Mixed-signal integrated circuit","level":3,"score":0.44501248002052307},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.22744473814964294},{"id":"https://openalex.org/C33923547","wikidata":"https://www.wikidata.org/wiki/Q395","display_name":"Mathematics","level":0,"score":0.21435365080833435},{"id":"https://openalex.org/C119599485","wikidata":"https://www.wikidata.org/wiki/Q43035","display_name":"Electrical engineering","level":1,"score":0.2047133445739746},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.14219895005226135},{"id":"https://openalex.org/C124101348","wikidata":"https://www.wikidata.org/wiki/Q172491","display_name":"Data mining","level":1,"score":0.13163694739341736},{"id":"https://openalex.org/C199360897","wikidata":"https://www.wikidata.org/wiki/Q9143","display_name":"Programming language","level":1,"score":0.07685104012489319},{"id":"https://openalex.org/C121332964","wikidata":"https://www.wikidata.org/wiki/Q413","display_name":"Physics","level":0,"score":0.06416794657707214},{"id":"https://openalex.org/C62520636","wikidata":"https://www.wikidata.org/wiki/Q944","display_name":"Quantum mechanics","level":1,"score":0.0},{"id":"https://openalex.org/C2524010","wikidata":"https://www.wikidata.org/wiki/Q8087","display_name":"Geometry","level":1,"score":0.0},{"id":"https://openalex.org/C111919701","wikidata":"https://www.wikidata.org/wiki/Q9135","display_name":"Operating system","level":1,"score":0.0},{"id":"https://openalex.org/C165801399","wikidata":"https://www.wikidata.org/wiki/Q25428","display_name":"Voltage","level":2,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/iscas.1994.408778","is_oa":false,"landing_page_url":"https://doi.org/10.1109/iscas.1994.408778","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"1994 IEEE International Symposium on Circuits and Systems (ISCAS)","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[],"awards":[],"funders":[],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":7,"referenced_works":["https://openalex.org/W13131068","https://openalex.org/W1551800824","https://openalex.org/W2034821239","https://openalex.org/W2135658286","https://openalex.org/W2152878140","https://openalex.org/W2153481183","https://openalex.org/W3016071238"],"related_works":["https://openalex.org/W2031235560","https://openalex.org/W2161335888","https://openalex.org/W2114773158","https://openalex.org/W4242383160","https://openalex.org/W2548106609","https://openalex.org/W2154989823","https://openalex.org/W1957521530","https://openalex.org/W1917800633","https://openalex.org/W2266281062","https://openalex.org/W1852277090"],"abstract_inverted_index":{"This":[0],"paper":[1],"describes":[2],"/spl":[3,28],"plusmn//spl":[4,29],"sigma/":[5,30],"transistor":[6,31],"modeling":[7],"and":[8,39,42],"its":[9],"application":[10],"in":[11],"worst":[12],"case":[13],"design":[14,38],"of":[15],"digital":[16],"integrated":[17],"circuits.":[18],"We":[19],"explore":[20],"the":[21,27,34,44,49,61],"implicit":[22],"assumptions":[23],"made":[24],"when":[25],"using":[26],"model,":[32],"establish":[33],"relationship":[35],"between":[36],"worst-case":[37,50],"variability":[40,45],"minimization,":[41],"extend":[43],"minimization":[46],"principles":[47],"to":[48,59],"measure":[51],"reduction.":[52],"A":[53],"CMOS":[54],"delay":[55],"circuit":[56],"is":[57],"used":[58],"clarify":[60],"discussion.<":[62],"<ETX":[63],"xmlns:mml=\"http://www.w3.org/1998/Math/MathML\"":[64],"xmlns:xlink=\"http://www.w3.org/1999/xlink\">&gt;</ETX>":[65]},"counts_by_year":[{"year":2016,"cited_by_count":1}],"updated_date":"2026-03-25T13:04:00.132906","created_date":"2025-10-10T00:00:00"}