{"id":"https://openalex.org/W4243620812","doi":"https://doi.org/10.1109/isca.2002.1003580","title":"Implementing optimizations at decode time","display_name":"Implementing optimizations at decode time","publication_year":2003,"publication_date":"2003-06-25","ids":{"openalex":"https://openalex.org/W4243620812","doi":"https://doi.org/10.1109/isca.2002.1003580"},"language":"en","primary_location":{"id":"doi:10.1109/isca.2002.1003580","is_oa":false,"landing_page_url":"https://doi.org/10.1109/isca.2002.1003580","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Proceedings 29th Annual International Symposium on Computer Architecture","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5013367702","display_name":"Ilhyun Kim","orcid":"https://orcid.org/0000-0003-4718-0590"},"institutions":[{"id":"https://openalex.org/I135310074","display_name":"University of Wisconsin\u2013Madison","ror":"https://ror.org/01y2jtd41","country_code":"US","type":"education","lineage":["https://openalex.org/I135310074"]}],"countries":["US"],"is_corresponding":true,"raw_author_name":"Ilhyun Kim","raw_affiliation_strings":["Department of Electrical and Computer Engineering, University of Wisconsin, Madison, USA"],"affiliations":[{"raw_affiliation_string":"Department of Electrical and Computer Engineering, University of Wisconsin, Madison, USA","institution_ids":["https://openalex.org/I135310074"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5075910905","display_name":"M.H. Lipasti","orcid":null},"institutions":[{"id":"https://openalex.org/I135310074","display_name":"University of Wisconsin\u2013Madison","ror":"https://ror.org/01y2jtd41","country_code":"US","type":"education","lineage":["https://openalex.org/I135310074"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"M.H. Lipasti","raw_affiliation_strings":["Department of Electrical and Computer Engineering, University of Wisconsin, Madison, USA"],"affiliations":[{"raw_affiliation_string":"Department of Electrical and Computer Engineering, University of Wisconsin, Madison, USA","institution_ids":["https://openalex.org/I135310074"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":2,"corresponding_author_ids":["https://openalex.org/A5013367702"],"corresponding_institution_ids":["https://openalex.org/I135310074"],"apc_list":null,"apc_paid":null,"fwci":0.47952827,"has_fulltext":false,"cited_by_count":5,"citation_normalized_percentile":{"value":0.68579967,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":89,"max":94},"biblio":{"volume":null,"issue":null,"first_page":"221","last_page":"232"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10904","display_name":"Embedded Systems Design Techniques","score":0.5533000230789185,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10904","display_name":"Embedded Systems Design Techniques","score":0.5533000230789185,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.9029408097267151},{"id":"https://openalex.org/keywords/scheduling","display_name":"Scheduling (production processes)","score":0.631689727306366},{"id":"https://openalex.org/keywords/latency","display_name":"Latency (audio)","score":0.6287972331047058},{"id":"https://openalex.org/keywords/speculative-execution","display_name":"Speculative execution","score":0.603176474571228},{"id":"https://openalex.org/keywords/implementation","display_name":"Implementation","score":0.556473970413208},{"id":"https://openalex.org/keywords/parallel-computing","display_name":"Parallel computing","score":0.5558668375015259},{"id":"https://openalex.org/keywords/instruction-scheduling","display_name":"Instruction scheduling","score":0.4981961250305176},{"id":"https://openalex.org/keywords/out-of-order-execution","display_name":"Out-of-order execution","score":0.4565051198005676},{"id":"https://openalex.org/keywords/dynamic-priority-scheduling","display_name":"Dynamic priority scheduling","score":0.44872161746025085},{"id":"https://openalex.org/keywords/microprocessor","display_name":"Microprocessor","score":0.4404544532299042},{"id":"https://openalex.org/keywords/distributed-computing","display_name":"Distributed computing","score":0.42025429010391235},{"id":"https://openalex.org/keywords/multi-core-processor","display_name":"Multi-core processor","score":0.41569432616233826},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.3221222758293152},{"id":"https://openalex.org/keywords/operating-system","display_name":"Operating system","score":0.23921623826026917},{"id":"https://openalex.org/keywords/schedule","display_name":"Schedule","score":0.20811337232589722},{"id":"https://openalex.org/keywords/two-level-scheduling","display_name":"Two-level scheduling","score":0.14980542659759521},{"id":"https://openalex.org/keywords/programming-language","display_name":"Programming language","score":0.1004696786403656}],"concepts":[{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.9029408097267151},{"id":"https://openalex.org/C206729178","wikidata":"https://www.wikidata.org/wiki/Q2271896","display_name":"Scheduling (production processes)","level":2,"score":0.631689727306366},{"id":"https://openalex.org/C82876162","wikidata":"https://www.wikidata.org/wiki/Q17096504","display_name":"Latency (audio)","level":2,"score":0.6287972331047058},{"id":"https://openalex.org/C141331961","wikidata":"https://www.wikidata.org/wiki/Q2164465","display_name":"Speculative execution","level":2,"score":0.603176474571228},{"id":"https://openalex.org/C26713055","wikidata":"https://www.wikidata.org/wiki/Q245962","display_name":"Implementation","level":2,"score":0.556473970413208},{"id":"https://openalex.org/C173608175","wikidata":"https://www.wikidata.org/wiki/Q232661","display_name":"Parallel computing","level":1,"score":0.5558668375015259},{"id":"https://openalex.org/C73564150","wikidata":"https://www.wikidata.org/wiki/Q11417093","display_name":"Instruction scheduling","level":5,"score":0.4981961250305176},{"id":"https://openalex.org/C1793878","wikidata":"https://www.wikidata.org/wiki/Q1153762","display_name":"Out-of-order execution","level":2,"score":0.4565051198005676},{"id":"https://openalex.org/C107568181","wikidata":"https://www.wikidata.org/wiki/Q5319000","display_name":"Dynamic priority scheduling","level":3,"score":0.44872161746025085},{"id":"https://openalex.org/C2780728072","wikidata":"https://www.wikidata.org/wiki/Q5297","display_name":"Microprocessor","level":2,"score":0.4404544532299042},{"id":"https://openalex.org/C120314980","wikidata":"https://www.wikidata.org/wiki/Q180634","display_name":"Distributed computing","level":1,"score":0.42025429010391235},{"id":"https://openalex.org/C78766204","wikidata":"https://www.wikidata.org/wiki/Q555032","display_name":"Multi-core processor","level":2,"score":0.41569432616233826},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.3221222758293152},{"id":"https://openalex.org/C111919701","wikidata":"https://www.wikidata.org/wiki/Q9135","display_name":"Operating system","level":1,"score":0.23921623826026917},{"id":"https://openalex.org/C68387754","wikidata":"https://www.wikidata.org/wiki/Q7271585","display_name":"Schedule","level":2,"score":0.20811337232589722},{"id":"https://openalex.org/C119948110","wikidata":"https://www.wikidata.org/wiki/Q7858726","display_name":"Two-level scheduling","level":4,"score":0.14980542659759521},{"id":"https://openalex.org/C199360897","wikidata":"https://www.wikidata.org/wiki/Q9143","display_name":"Programming language","level":1,"score":0.1004696786403656},{"id":"https://openalex.org/C76155785","wikidata":"https://www.wikidata.org/wiki/Q418","display_name":"Telecommunications","level":1,"score":0.0},{"id":"https://openalex.org/C162324750","wikidata":"https://www.wikidata.org/wiki/Q8134","display_name":"Economics","level":0,"score":0.0},{"id":"https://openalex.org/C21547014","wikidata":"https://www.wikidata.org/wiki/Q1423657","display_name":"Operations management","level":1,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/isca.2002.1003580","is_oa":false,"landing_page_url":"https://doi.org/10.1109/isca.2002.1003580","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Proceedings 29th Annual International Symposium on Computer Architecture","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[],"awards":[],"funders":[{"id":"https://openalex.org/F4320306076","display_name":"National Science Foundation","ror":"https://ror.org/021nxhr62"}],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":20,"referenced_works":["https://openalex.org/W63944998","https://openalex.org/W1506762940","https://openalex.org/W1555915743","https://openalex.org/W1965562075","https://openalex.org/W2005343162","https://openalex.org/W2032094184","https://openalex.org/W2038037303","https://openalex.org/W2060480557","https://openalex.org/W2129760904","https://openalex.org/W2135885084","https://openalex.org/W2144334298","https://openalex.org/W2155861433","https://openalex.org/W2170585292","https://openalex.org/W2916411819","https://openalex.org/W4231307773","https://openalex.org/W4232645751","https://openalex.org/W4233348269","https://openalex.org/W4249929199","https://openalex.org/W6602613798","https://openalex.org/W6759615093"],"related_works":["https://openalex.org/W37057355","https://openalex.org/W2897302968","https://openalex.org/W2099786221","https://openalex.org/W1889544578","https://openalex.org/W1532214443","https://openalex.org/W2334517886","https://openalex.org/W1506303948","https://openalex.org/W2100519017","https://openalex.org/W4243620812","https://openalex.org/W2113189450"],"abstract_inverted_index":{"The":[0],"number":[1],"of":[2],"pipeline":[3],"stages":[4],"separating":[5],"dynamic":[6,69,90],"instruction":[7,10,74,131],"scheduling":[8,83,148,179],"from":[9],"execution":[11,29,61],"has":[12],"increased":[13],"considerably":[14],"in":[15,49,60,66,139],"recent":[16],"out-of-order":[17],"microprocessor":[18],"implementations,":[19],"forcing":[20],"the":[21,113,119],"scheduler":[22],"to":[23,68,100],"allocate":[24],"functional":[25],"units":[26],"and":[27,63,118,128,158,162],"other":[28],"resources":[30],"several":[31,39,80],"cycles":[32,81],"before,":[33],"they":[34,54,77],"are":[35,78,92,137],"actually":[36],"used.":[37],"Unfortunately,":[38],"proposed":[40],"microarchitectural":[41],"optimizations":[42,102,136],"become":[43],"less":[44],"desirable":[45],"or":[46,57,169],"even":[47,170],"impossible":[48],"such":[50,89],"an":[51],"environment,":[52],"since":[53],"require":[55,177],"instantaneous":[56],"near-instantaneous":[58],"changes":[59],"behavior":[62],"resource":[64],"usage":[65],"response":[67],"events":[70],"that":[71,164,176],"occur":[72],"during":[73],"execution.":[75],"Since":[76],"detected":[79],"after":[82],"decisions":[84],"have":[85],"already":[86],"been":[87],"made,":[88],"responses":[91],"infeasible.":[93],"To":[94],"overcome":[95],"this":[96],"limitation,":[97],"we":[98,106],"propose":[99],"implement":[101],"by":[103],"performing":[104],"what":[105],"call":[107],"speculative":[108,130,165],"decode.":[109],"Speculative":[110],"decode":[111,166],"alters":[112],"mapping":[114],"between":[115],"user-visible":[116],"instructions":[117,122],"implemented":[120],"core":[121],"based":[123],"on":[124,154],"observed":[125],"runtime":[126],"characteristics":[127],"generates":[129],"sequences.":[132],"In":[133],"these":[134],"sequences,":[135],"pre-scheduled":[138],"a":[140],"manner":[141],"compatible":[142],"with":[143,146],"realistic":[144],"pipelines":[145],"multicycle":[147],"latency.":[149,180],"We":[150],"present":[151],"case":[152],"studies":[153],"memory":[155],"reference":[156],"combining":[157],"silent":[159],"store":[160],"squashing,":[161],"demonstrate":[163],"performs":[167],"comparably":[168],"better":[171],"than":[172],"impractical":[173],"in-core":[174],"implementations":[175],"zero-cycle":[178]},"counts_by_year":[{"year":2024,"cited_by_count":1},{"year":2022,"cited_by_count":1},{"year":2017,"cited_by_count":1}],"updated_date":"2025-11-06T03:46:38.306776","created_date":"2025-10-10T00:00:00"}
