{"id":"https://openalex.org/W4254589276","doi":"https://doi.org/10.1109/isca.2002.1003576","title":"Using a user-level memory thread for correlation prefetching","display_name":"Using a user-level memory thread for correlation prefetching","publication_year":2003,"publication_date":"2003-06-25","ids":{"openalex":"https://openalex.org/W4254589276","doi":"https://doi.org/10.1109/isca.2002.1003576"},"language":"en","primary_location":{"id":"doi:10.1109/isca.2002.1003576","is_oa":false,"landing_page_url":"https://doi.org/10.1109/isca.2002.1003576","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Proceedings 29th Annual International Symposium on Computer Architecture","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5061775189","display_name":"Yan Solihin","orcid":"https://orcid.org/0000-0002-8863-941X"},"institutions":[{"id":"https://openalex.org/I157725225","display_name":"University of Illinois Urbana-Champaign","ror":"https://ror.org/047426m28","country_code":"US","type":"education","lineage":["https://openalex.org/I157725225"]}],"countries":["US"],"is_corresponding":true,"raw_author_name":"Y. Solihin","raw_affiliation_strings":["University of Illinois, Urbana-Champaign, USA"],"affiliations":[{"raw_affiliation_string":"University of Illinois, Urbana-Champaign, USA","institution_ids":["https://openalex.org/I157725225"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5100767182","display_name":"Jaejin Lee","orcid":"https://orcid.org/0000-0003-4638-8170"},"institutions":[{"id":"https://openalex.org/I87216513","display_name":"Michigan State University","ror":"https://ror.org/05hs6h993","country_code":"US","type":"education","lineage":["https://openalex.org/I87216513"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Jaejin Lee","raw_affiliation_strings":["Michigan State University, USA"],"affiliations":[{"raw_affiliation_string":"Michigan State University, USA","institution_ids":["https://openalex.org/I87216513"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5055909708","display_name":"Josep Torrellas","orcid":"https://orcid.org/0000-0003-2595-5228"},"institutions":[{"id":"https://openalex.org/I157725225","display_name":"University of Illinois Urbana-Champaign","ror":"https://ror.org/047426m28","country_code":"US","type":"education","lineage":["https://openalex.org/I157725225"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"J. Torrellas","raw_affiliation_strings":["University of Illinois, Urbana-Champaign, USA"],"affiliations":[{"raw_affiliation_string":"University of Illinois, Urbana-Champaign, USA","institution_ids":["https://openalex.org/I157725225"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":3,"corresponding_author_ids":["https://openalex.org/A5061775189"],"corresponding_institution_ids":["https://openalex.org/I157725225"],"apc_list":null,"apc_paid":null,"fwci":5.534,"has_fulltext":false,"cited_by_count":86,"citation_normalized_percentile":{"value":0.96268875,"is_in_top_1_percent":false,"is_in_top_10_percent":true},"cited_by_percentile_year":{"min":89,"max":99},"biblio":{"volume":null,"issue":null,"first_page":"171","last_page":"182"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10054","display_name":"Parallel Computing and Optimization Techniques","score":1.0,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10054","display_name":"Parallel Computing and Optimization Techniques","score":1.0,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11181","display_name":"Advanced Data Storage Technologies","score":0.9995999932289124,"subfield":{"id":"https://openalex.org/subfields/1705","display_name":"Computer Networks and Communications"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10829","display_name":"Interconnection Networks and Systems","score":0.9991000294685364,"subfield":{"id":"https://openalex.org/subfields/1705","display_name":"Computer Networks and Communications"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.8680124282836914},{"id":"https://openalex.org/keywords/instruction-prefetch","display_name":"Instruction prefetch","score":0.8312366008758545},{"id":"https://openalex.org/keywords/speedup","display_name":"Speedup","score":0.7526843547821045},{"id":"https://openalex.org/keywords/parallel-computing","display_name":"Parallel computing","score":0.7462244033813477},{"id":"https://openalex.org/keywords/thread","display_name":"Thread (computing)","score":0.6374225616455078},{"id":"https://openalex.org/keywords/cache","display_name":"Cache","score":0.5675495266914368},{"id":"https://openalex.org/keywords/cas-latency","display_name":"CAS latency","score":0.5144879817962646},{"id":"https://openalex.org/keywords/multithreading","display_name":"Multithreading","score":0.4477446675300598},{"id":"https://openalex.org/keywords/software","display_name":"Software","score":0.4188710153102875},{"id":"https://openalex.org/keywords/memory-controller","display_name":"Memory controller","score":0.31073686480522156},{"id":"https://openalex.org/keywords/computer-hardware","display_name":"Computer hardware","score":0.28232336044311523},{"id":"https://openalex.org/keywords/operating-system","display_name":"Operating system","score":0.2517980635166168},{"id":"https://openalex.org/keywords/semiconductor-memory","display_name":"Semiconductor memory","score":0.14680215716362}],"concepts":[{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.8680124282836914},{"id":"https://openalex.org/C133588205","wikidata":"https://www.wikidata.org/wiki/Q28455645","display_name":"Instruction prefetch","level":3,"score":0.8312366008758545},{"id":"https://openalex.org/C68339613","wikidata":"https://www.wikidata.org/wiki/Q1549489","display_name":"Speedup","level":2,"score":0.7526843547821045},{"id":"https://openalex.org/C173608175","wikidata":"https://www.wikidata.org/wiki/Q232661","display_name":"Parallel computing","level":1,"score":0.7462244033813477},{"id":"https://openalex.org/C138101251","wikidata":"https://www.wikidata.org/wiki/Q213092","display_name":"Thread (computing)","level":2,"score":0.6374225616455078},{"id":"https://openalex.org/C115537543","wikidata":"https://www.wikidata.org/wiki/Q165596","display_name":"Cache","level":2,"score":0.5675495266914368},{"id":"https://openalex.org/C189930140","wikidata":"https://www.wikidata.org/wiki/Q1112878","display_name":"CAS latency","level":4,"score":0.5144879817962646},{"id":"https://openalex.org/C201410400","wikidata":"https://www.wikidata.org/wiki/Q1064412","display_name":"Multithreading","level":3,"score":0.4477446675300598},{"id":"https://openalex.org/C2777904410","wikidata":"https://www.wikidata.org/wiki/Q7397","display_name":"Software","level":2,"score":0.4188710153102875},{"id":"https://openalex.org/C100800780","wikidata":"https://www.wikidata.org/wiki/Q1175867","display_name":"Memory controller","level":3,"score":0.31073686480522156},{"id":"https://openalex.org/C9390403","wikidata":"https://www.wikidata.org/wiki/Q3966","display_name":"Computer hardware","level":1,"score":0.28232336044311523},{"id":"https://openalex.org/C111919701","wikidata":"https://www.wikidata.org/wiki/Q9135","display_name":"Operating system","level":1,"score":0.2517980635166168},{"id":"https://openalex.org/C98986596","wikidata":"https://www.wikidata.org/wiki/Q1143031","display_name":"Semiconductor memory","level":2,"score":0.14680215716362}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/isca.2002.1003576","is_oa":false,"landing_page_url":"https://doi.org/10.1109/isca.2002.1003576","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Proceedings 29th Annual International Symposium on Computer Architecture","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[],"awards":[],"funders":[],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":24,"referenced_works":["https://openalex.org/W1530158005","https://openalex.org/W2028917428","https://openalex.org/W2072147656","https://openalex.org/W2092291350","https://openalex.org/W2095679548","https://openalex.org/W2097215759","https://openalex.org/W2107354725","https://openalex.org/W2110815624","https://openalex.org/W2122060420","https://openalex.org/W2122234783","https://openalex.org/W2123278124","https://openalex.org/W2128104279","https://openalex.org/W2152356827","https://openalex.org/W2153515302","https://openalex.org/W4237150160","https://openalex.org/W4240365740","https://openalex.org/W4241924712","https://openalex.org/W4243147462","https://openalex.org/W4246178214","https://openalex.org/W4248446132","https://openalex.org/W4251077909","https://openalex.org/W6631570430","https://openalex.org/W6678056560","https://openalex.org/W6679019147"],"related_works":["https://openalex.org/W2010970156","https://openalex.org/W4235861380","https://openalex.org/W2106625514","https://openalex.org/W1586800019","https://openalex.org/W1991593386","https://openalex.org/W4250937590","https://openalex.org/W2133693067","https://openalex.org/W177783857","https://openalex.org/W3033052750","https://openalex.org/W2166609549"],"abstract_inverted_index":{"This":[0,59],"paper":[1],"introduces":[2],"the":[3,31,48,52,56,65,68,79,83,104,124,131,147,184,193,196,201],"idea":[4],"of":[5,55,146,166,195],"using":[6],"a":[7,18,23,37,72,88,143,176],"user-level":[8],"memory":[9,32,66],"thread":[10,20,41],"(ULMT)":[11],"for":[12,115],"correlation":[13,43,69,148],"prefetching.":[14],"In":[15,102],"this":[16],"approach,":[17],"user":[19,132],"runs":[21],"on":[22,133],"general-purpose":[24],"processor":[25,85],"in":[26,30,36,45,78,173,181],"main":[27,57,80,84],"memory,":[28,81],"either":[29],"controller":[33],"chip":[34],"or":[35],"DRAM":[38],"chip.":[39],"The":[40],"performs":[42],"prefetching":[44,125,151,197],"software,":[46],"sending":[47],"prefetched":[49],"data":[50,74],"into":[51],"L2":[53,93],"cache":[54,94],"processor.":[58],"approach":[60,105],"requires":[61],"minimal":[62],"hardware":[63],"beyond":[64],"processor:":[67],"table":[70,149],"is":[71,120],"software":[73],"structure":[75],"that":[76,96],"resides":[77],"while":[82],"only":[86],"needs":[87],"few":[89],"modifications":[90],"to":[91,188,205],"its":[92],"so":[95],"it":[97,110,119],"can":[98,111,127],"accept":[99],"incoming":[100],"prefetches.":[101],"addition,":[103],"has":[106],"wide":[107],"usability,":[108],"as":[109,123],"effectively":[112],"prefetch":[113],"even":[114],"irregular":[116],"applications.":[117],"Finally,":[118,190],"very":[121],"flexible,":[122],"algorithm":[126],"be":[128],"customized":[129],"by":[130,191],"an":[134,163],"application":[135],"basis.":[136],"Our":[137],"simulation":[138],"results":[139],"show":[140,162],"that,":[141],"through":[142],"new":[144],"design":[145],"and":[150],"algorithm,":[152,198],"our":[153,169],"scheme":[154,170],"delivers":[155],"good":[156],"results.":[157],"Specifically,":[158],"nine":[159],"mostly-irregular":[160],"applications":[161],"average":[164,185,202],"speedup":[165,186],"1.32.":[167],"Furthermore,":[168],"works":[171],"well":[172],"combination":[174],"with":[175],"conventional":[177],"processor-side":[178],"sequential":[179],"prefetcher,":[180],"which":[182],"case":[183],"increases":[187],"1.46.":[189],"exploiting":[192],"customization":[194],"we":[199],"increase":[200],"speed":[203],"up":[204],"1.53.":[206]},"counts_by_year":[{"year":2026,"cited_by_count":1},{"year":2025,"cited_by_count":1},{"year":2024,"cited_by_count":4},{"year":2023,"cited_by_count":1},{"year":2022,"cited_by_count":8},{"year":2021,"cited_by_count":3},{"year":2020,"cited_by_count":3},{"year":2019,"cited_by_count":5},{"year":2018,"cited_by_count":1},{"year":2017,"cited_by_count":2},{"year":2016,"cited_by_count":4},{"year":2015,"cited_by_count":3},{"year":2014,"cited_by_count":3},{"year":2013,"cited_by_count":1},{"year":2012,"cited_by_count":5}],"updated_date":"2026-02-07T06:11:34.122080","created_date":"2025-10-10T00:00:00"}