{"id":"https://openalex.org/W1533965610","doi":"https://doi.org/10.1109/irps.2015.7112692","title":"Transistor aging and reliability in 14nm tri-gate technology","display_name":"Transistor aging and reliability in 14nm tri-gate technology","publication_year":2015,"publication_date":"2015-04-01","ids":{"openalex":"https://openalex.org/W1533965610","doi":"https://doi.org/10.1109/irps.2015.7112692","mag":"1533965610"},"language":"en","primary_location":{"id":"doi:10.1109/irps.2015.7112692","is_oa":false,"landing_page_url":"https://doi.org/10.1109/irps.2015.7112692","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2015 IEEE International Reliability Physics Symposium","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5079033229","display_name":"S. Novak","orcid":null},"institutions":[{"id":"https://openalex.org/I1343180700","display_name":"Intel (United States)","ror":"https://ror.org/01ek73717","country_code":"US","type":"company","lineage":["https://openalex.org/I1343180700"]}],"countries":["US"],"is_corresponding":true,"raw_author_name":"S. Novak","raw_affiliation_strings":["Logic Technology Development Quality and Reliability, Portland Technology Development Intel Corp., Hillsboro, Oregon, U.S.A","Logic Technology Development Quality and Reliability, Portland Technology Development, Intel Corp. Hillsboro, Oregon, U.S.A"],"affiliations":[{"raw_affiliation_string":"Logic Technology Development Quality and Reliability, Portland Technology Development Intel Corp., Hillsboro, Oregon, U.S.A","institution_ids":["https://openalex.org/I1343180700"]},{"raw_affiliation_string":"Logic Technology Development Quality and Reliability, Portland Technology Development, Intel Corp. Hillsboro, Oregon, U.S.A","institution_ids":["https://openalex.org/I1343180700"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5035806887","display_name":"C. Parker","orcid":"https://orcid.org/0009-0001-9937-228X"},"institutions":[{"id":"https://openalex.org/I1343180700","display_name":"Intel (United States)","ror":"https://ror.org/01ek73717","country_code":"US","type":"company","lineage":["https://openalex.org/I1343180700"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"C. Parker","raw_affiliation_strings":["Logic Technology Development Quality and Reliability, Portland Technology Development Intel Corp., Hillsboro, Oregon, U.S.A","Logic Technology Development Quality and Reliability, Portland Technology Development, Intel Corp. Hillsboro, Oregon, U.S.A"],"affiliations":[{"raw_affiliation_string":"Logic Technology Development Quality and Reliability, Portland Technology Development Intel Corp., Hillsboro, Oregon, U.S.A","institution_ids":["https://openalex.org/I1343180700"]},{"raw_affiliation_string":"Logic Technology Development Quality and Reliability, Portland Technology Development, Intel Corp. Hillsboro, Oregon, U.S.A","institution_ids":["https://openalex.org/I1343180700"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5021202027","display_name":"D. Becher","orcid":null},"institutions":[{"id":"https://openalex.org/I1343180700","display_name":"Intel (United States)","ror":"https://ror.org/01ek73717","country_code":"US","type":"company","lineage":["https://openalex.org/I1343180700"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"D. Becher","raw_affiliation_strings":["Logic Technology Development Quality and Reliability, Portland Technology Development Intel Corp., Hillsboro, Oregon, U.S.A","Logic Technology Development Quality and Reliability, Portland Technology Development, Intel Corp. Hillsboro, Oregon, U.S.A"],"affiliations":[{"raw_affiliation_string":"Logic Technology Development Quality and Reliability, Portland Technology Development Intel Corp., Hillsboro, Oregon, U.S.A","institution_ids":["https://openalex.org/I1343180700"]},{"raw_affiliation_string":"Logic Technology Development Quality and Reliability, Portland Technology Development, Intel Corp. Hillsboro, Oregon, U.S.A","institution_ids":["https://openalex.org/I1343180700"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5049908114","display_name":"Miao Liu","orcid":"https://orcid.org/0009-0008-7757-2257"},"institutions":[{"id":"https://openalex.org/I1343180700","display_name":"Intel (United States)","ror":"https://ror.org/01ek73717","country_code":"US","type":"company","lineage":["https://openalex.org/I1343180700"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"M. Liu","raw_affiliation_strings":["Logic Technology Development Quality and Reliability, Portland Technology Development Intel Corp., Hillsboro, Oregon, U.S.A","Logic Technology Development Quality and Reliability, Portland Technology Development, Intel Corp. Hillsboro, Oregon, U.S.A"],"affiliations":[{"raw_affiliation_string":"Logic Technology Development Quality and Reliability, Portland Technology Development Intel Corp., Hillsboro, Oregon, U.S.A","institution_ids":["https://openalex.org/I1343180700"]},{"raw_affiliation_string":"Logic Technology Development Quality and Reliability, Portland Technology Development, Intel Corp. Hillsboro, Oregon, U.S.A","institution_ids":["https://openalex.org/I1343180700"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5046921366","display_name":"M. Agostinelli","orcid":null},"institutions":[{"id":"https://openalex.org/I1343180700","display_name":"Intel (United States)","ror":"https://ror.org/01ek73717","country_code":"US","type":"company","lineage":["https://openalex.org/I1343180700"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"M. Agostinelli","raw_affiliation_strings":["Logic Technology Development Quality and Reliability, Portland Technology Development Intel Corp., Hillsboro, Oregon, U.S.A","Logic Technology Development Quality and Reliability, Portland Technology Development, Intel Corp. Hillsboro, Oregon, U.S.A"],"affiliations":[{"raw_affiliation_string":"Logic Technology Development Quality and Reliability, Portland Technology Development Intel Corp., Hillsboro, Oregon, U.S.A","institution_ids":["https://openalex.org/I1343180700"]},{"raw_affiliation_string":"Logic Technology Development Quality and Reliability, Portland Technology Development, Intel Corp. Hillsboro, Oregon, U.S.A","institution_ids":["https://openalex.org/I1343180700"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5003409489","display_name":"Manisha Chahal","orcid":"https://orcid.org/0000-0003-4727-0561"},"institutions":[{"id":"https://openalex.org/I1343180700","display_name":"Intel (United States)","ror":"https://ror.org/01ek73717","country_code":"US","type":"company","lineage":["https://openalex.org/I1343180700"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"M. Chahal","raw_affiliation_strings":["Logic Technology Development Quality and Reliability, Portland Technology Development Intel Corp., Hillsboro, Oregon, U.S.A","Logic Technology Development Quality and Reliability, Portland Technology Development, Intel Corp. Hillsboro, Oregon, U.S.A"],"affiliations":[{"raw_affiliation_string":"Logic Technology Development Quality and Reliability, Portland Technology Development Intel Corp., Hillsboro, Oregon, U.S.A","institution_ids":["https://openalex.org/I1343180700"]},{"raw_affiliation_string":"Logic Technology Development Quality and Reliability, Portland Technology Development, Intel Corp. Hillsboro, Oregon, U.S.A","institution_ids":["https://openalex.org/I1343180700"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5069755352","display_name":"P. Packan","orcid":null},"institutions":[{"id":"https://openalex.org/I1343180700","display_name":"Intel (United States)","ror":"https://ror.org/01ek73717","country_code":"US","type":"company","lineage":["https://openalex.org/I1343180700"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"P. Packan","raw_affiliation_strings":["Logic Technology Development Quality and Reliability, Portland Technology Development Intel Corp., Hillsboro, Oregon, U.S.A","Logic Technology Development Quality and Reliability, Portland Technology Development, Intel Corp. Hillsboro, Oregon, U.S.A"],"affiliations":[{"raw_affiliation_string":"Logic Technology Development Quality and Reliability, Portland Technology Development Intel Corp., Hillsboro, Oregon, U.S.A","institution_ids":["https://openalex.org/I1343180700"]},{"raw_affiliation_string":"Logic Technology Development Quality and Reliability, Portland Technology Development, Intel Corp. Hillsboro, Oregon, U.S.A","institution_ids":["https://openalex.org/I1343180700"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5112779576","display_name":"P. Nayak","orcid":null},"institutions":[{"id":"https://openalex.org/I1343180700","display_name":"Intel (United States)","ror":"https://ror.org/01ek73717","country_code":"US","type":"company","lineage":["https://openalex.org/I1343180700"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"P. Nayak","raw_affiliation_strings":["Logic Technology Development Quality and Reliability, Portland Technology Development Intel Corp., Hillsboro, Oregon, U.S.A","Logic Technology Development Quality and Reliability, Portland Technology Development, Intel Corp. Hillsboro, Oregon, U.S.A"],"affiliations":[{"raw_affiliation_string":"Logic Technology Development Quality and Reliability, Portland Technology Development Intel Corp., Hillsboro, Oregon, U.S.A","institution_ids":["https://openalex.org/I1343180700"]},{"raw_affiliation_string":"Logic Technology Development Quality and Reliability, Portland Technology Development, Intel Corp. Hillsboro, Oregon, U.S.A","institution_ids":["https://openalex.org/I1343180700"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5027832758","display_name":"S. Ramey","orcid":null},"institutions":[{"id":"https://openalex.org/I1343180700","display_name":"Intel (United States)","ror":"https://ror.org/01ek73717","country_code":"US","type":"company","lineage":["https://openalex.org/I1343180700"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"S. Ramey","raw_affiliation_strings":["Logic Technology Development Quality and Reliability, Portland Technology Development Intel Corp., Hillsboro, Oregon, U.S.A","Logic Technology Development Quality and Reliability, Portland Technology Development, Intel Corp. Hillsboro, Oregon, U.S.A"],"affiliations":[{"raw_affiliation_string":"Logic Technology Development Quality and Reliability, Portland Technology Development Intel Corp., Hillsboro, Oregon, U.S.A","institution_ids":["https://openalex.org/I1343180700"]},{"raw_affiliation_string":"Logic Technology Development Quality and Reliability, Portland Technology Development, Intel Corp. Hillsboro, Oregon, U.S.A","institution_ids":["https://openalex.org/I1343180700"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5027145012","display_name":"S. Natarajan","orcid":"https://orcid.org/0000-0002-8765-1038"},"institutions":[{"id":"https://openalex.org/I1343180700","display_name":"Intel (United States)","ror":"https://ror.org/01ek73717","country_code":"US","type":"company","lineage":["https://openalex.org/I1343180700"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"S. Natarajan","raw_affiliation_strings":["Logic Technology Development Quality and Reliability, Portland Technology Development Intel Corp., Hillsboro, Oregon, U.S.A","Logic Technology Development Quality and Reliability, Portland Technology Development, Intel Corp. Hillsboro, Oregon, U.S.A"],"affiliations":[{"raw_affiliation_string":"Logic Technology Development Quality and Reliability, Portland Technology Development Intel Corp., Hillsboro, Oregon, U.S.A","institution_ids":["https://openalex.org/I1343180700"]},{"raw_affiliation_string":"Logic Technology Development Quality and Reliability, Portland Technology Development, Intel Corp. Hillsboro, Oregon, U.S.A","institution_ids":["https://openalex.org/I1343180700"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":10,"corresponding_author_ids":["https://openalex.org/A5079033229"],"corresponding_institution_ids":["https://openalex.org/I1343180700"],"apc_list":null,"apc_paid":null,"fwci":5.1295,"has_fulltext":false,"cited_by_count":65,"citation_normalized_percentile":{"value":0.95671705,"is_in_top_1_percent":false,"is_in_top_10_percent":true},"cited_by_percentile_year":{"min":96,"max":99},"biblio":{"volume":null,"issue":null,"first_page":"2F.2.1","last_page":"2F.2.5"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10472","display_name":"Semiconductor materials and devices","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10472","display_name":"Semiconductor materials and devices","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10558","display_name":"Advancements in Semiconductor Devices and Circuit Design","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T12808","display_name":"Ferroelectric and Negative Capacitance Devices","score":0.9991999864578247,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/reliability","display_name":"Reliability (semiconductor)","score":0.7529711723327637},{"id":"https://openalex.org/keywords/transistor","display_name":"Transistor","score":0.6762667298316956},{"id":"https://openalex.org/keywords/metal-gate","display_name":"Metal gate","score":0.4853857755661011},{"id":"https://openalex.org/keywords/gate-dielectric","display_name":"Gate dielectric","score":0.4570486843585968},{"id":"https://openalex.org/keywords/scaling","display_name":"Scaling","score":0.43000805377960205},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.42458486557006836},{"id":"https://openalex.org/keywords/materials-science","display_name":"Materials science","score":0.3905303478240967},{"id":"https://openalex.org/keywords/electrical-engineering","display_name":"Electrical engineering","score":0.378167062997818},{"id":"https://openalex.org/keywords/gate-oxide","display_name":"Gate oxide","score":0.37749922275543213},{"id":"https://openalex.org/keywords/optoelectronics","display_name":"Optoelectronics","score":0.3394971489906311},{"id":"https://openalex.org/keywords/reliability-engineering","display_name":"Reliability engineering","score":0.3308471441268921},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.2439047396183014},{"id":"https://openalex.org/keywords/physics","display_name":"Physics","score":0.241074800491333},{"id":"https://openalex.org/keywords/mathematics","display_name":"Mathematics","score":0.08209919929504395}],"concepts":[{"id":"https://openalex.org/C43214815","wikidata":"https://www.wikidata.org/wiki/Q7310987","display_name":"Reliability (semiconductor)","level":3,"score":0.7529711723327637},{"id":"https://openalex.org/C172385210","wikidata":"https://www.wikidata.org/wiki/Q5339","display_name":"Transistor","level":3,"score":0.6762667298316956},{"id":"https://openalex.org/C51140833","wikidata":"https://www.wikidata.org/wiki/Q6822740","display_name":"Metal gate","level":5,"score":0.4853857755661011},{"id":"https://openalex.org/C166972891","wikidata":"https://www.wikidata.org/wiki/Q5527011","display_name":"Gate dielectric","level":4,"score":0.4570486843585968},{"id":"https://openalex.org/C99844830","wikidata":"https://www.wikidata.org/wiki/Q102441924","display_name":"Scaling","level":2,"score":0.43000805377960205},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.42458486557006836},{"id":"https://openalex.org/C192562407","wikidata":"https://www.wikidata.org/wiki/Q228736","display_name":"Materials science","level":0,"score":0.3905303478240967},{"id":"https://openalex.org/C119599485","wikidata":"https://www.wikidata.org/wiki/Q43035","display_name":"Electrical engineering","level":1,"score":0.378167062997818},{"id":"https://openalex.org/C2361726","wikidata":"https://www.wikidata.org/wiki/Q5527031","display_name":"Gate oxide","level":4,"score":0.37749922275543213},{"id":"https://openalex.org/C49040817","wikidata":"https://www.wikidata.org/wiki/Q193091","display_name":"Optoelectronics","level":1,"score":0.3394971489906311},{"id":"https://openalex.org/C200601418","wikidata":"https://www.wikidata.org/wiki/Q2193887","display_name":"Reliability engineering","level":1,"score":0.3308471441268921},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.2439047396183014},{"id":"https://openalex.org/C121332964","wikidata":"https://www.wikidata.org/wiki/Q413","display_name":"Physics","level":0,"score":0.241074800491333},{"id":"https://openalex.org/C33923547","wikidata":"https://www.wikidata.org/wiki/Q395","display_name":"Mathematics","level":0,"score":0.08209919929504395},{"id":"https://openalex.org/C2524010","wikidata":"https://www.wikidata.org/wiki/Q8087","display_name":"Geometry","level":1,"score":0.0},{"id":"https://openalex.org/C165801399","wikidata":"https://www.wikidata.org/wiki/Q25428","display_name":"Voltage","level":2,"score":0.0},{"id":"https://openalex.org/C163258240","wikidata":"https://www.wikidata.org/wiki/Q25342","display_name":"Power (physics)","level":2,"score":0.0},{"id":"https://openalex.org/C62520636","wikidata":"https://www.wikidata.org/wiki/Q944","display_name":"Quantum mechanics","level":1,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/irps.2015.7112692","is_oa":false,"landing_page_url":"https://doi.org/10.1109/irps.2015.7112692","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2015 IEEE International Reliability Physics Symposium","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[{"score":0.41999998688697815,"id":"https://metadata.un.org/sdg/7","display_name":"Affordable and clean energy"}],"awards":[],"funders":[],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":14,"referenced_works":["https://openalex.org/W1488749315","https://openalex.org/W1965229716","https://openalex.org/W1966797259","https://openalex.org/W1986824285","https://openalex.org/W1988922865","https://openalex.org/W1995863305","https://openalex.org/W2102769581","https://openalex.org/W2115073796","https://openalex.org/W2139666879","https://openalex.org/W2162517322","https://openalex.org/W2173999255","https://openalex.org/W6629258623","https://openalex.org/W6675399364","https://openalex.org/W6685244786"],"related_works":["https://openalex.org/W2084196976","https://openalex.org/W2796938634","https://openalex.org/W2064786169","https://openalex.org/W2020270409","https://openalex.org/W1971221880","https://openalex.org/W1623370118","https://openalex.org/W2585968548","https://openalex.org/W2532123035","https://openalex.org/W1553039458","https://openalex.org/W2115152876"],"abstract_inverted_index":{"This":[0,15],"paper":[1],"details":[2],"the":[3,27],"transistor":[4,25,49],"aging":[5],"and":[6,26,36],"gate":[7],"oxide":[8],"reliability":[9,40,45],"of":[10,33],"Intel's":[11,18],"14nm":[12],"process":[13],"technology.":[14],"technology":[16],"introduces":[17],"2":[19],"<sup":[20,29],"xmlns:mml=\"http://www.w3.org/1998/Math/MathML\"":[21,30],"xmlns:xlink=\"http://www.w3.org/1999/xlink\">nd</sup>":[22],"generation":[23,32],"tri-gate":[24],"4":[28],"xmlns:xlink=\"http://www.w3.org/1999/xlink\">th</sup>":[31],"high-\u03ba":[34],"dielectrics":[35],"metal-gate":[37],"electrodes.":[38],"The":[39],"metrics":[41],"reported":[42],"here":[43],"highlight":[44],"gains":[46],"attained":[47],"through":[48],"optimizations":[50],"as":[51,53],"well":[52],"intrinsic":[54],"challenges":[55],"from":[56],"device":[57],"scaling.":[58]},"counts_by_year":[{"year":2024,"cited_by_count":3},{"year":2023,"cited_by_count":5},{"year":2022,"cited_by_count":8},{"year":2021,"cited_by_count":7},{"year":2020,"cited_by_count":11},{"year":2019,"cited_by_count":5},{"year":2018,"cited_by_count":12},{"year":2017,"cited_by_count":4},{"year":2016,"cited_by_count":4},{"year":2015,"cited_by_count":6}],"updated_date":"2025-11-06T03:46:38.306776","created_date":"2025-10-10T00:00:00"}
