{"id":"https://openalex.org/W4254160515","doi":"https://doi.org/10.1109/ipdps.2004.1303140","title":"MemMap-pd: performance driven technology mapping algorithm for FPGAs with embedded memory arrays","display_name":"MemMap-pd: performance driven technology mapping algorithm for FPGAs with embedded memory arrays","publication_year":2004,"publication_date":"2004-06-10","ids":{"openalex":"https://openalex.org/W4254160515","doi":"https://doi.org/10.1109/ipdps.2004.1303140"},"language":"en","primary_location":{"id":"doi:10.1109/ipdps.2004.1303140","is_oa":false,"landing_page_url":"https://doi.org/10.1109/ipdps.2004.1303140","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"18th International Parallel and Distributed Processing Symposium, 2004. Proceedings.","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5001436195","display_name":"A.M. Kumar","orcid":null},"institutions":[{"id":"https://openalex.org/I24676775","display_name":"Indian Institute of Technology Madras","ror":"https://ror.org/03v0r5n49","country_code":"IN","type":"facility","lineage":["https://openalex.org/I24676775"]}],"countries":["IN"],"is_corresponding":true,"raw_author_name":"A.M. Kumar","raw_affiliation_strings":["Indian Institute of Technology Madras, Chennai, India"],"affiliations":[{"raw_affiliation_string":"Indian Institute of Technology Madras, Chennai, India","institution_ids":["https://openalex.org/I24676775"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5081114352","display_name":"B. Jayaram","orcid":null},"institutions":[{"id":"https://openalex.org/I24676775","display_name":"Indian Institute of Technology Madras","ror":"https://ror.org/03v0r5n49","country_code":"IN","type":"facility","lineage":["https://openalex.org/I24676775"]}],"countries":["IN"],"is_corresponding":false,"raw_author_name":"B. Jayaram","raw_affiliation_strings":["Indian Institute of Technology Madras, Chennai, India"],"affiliations":[{"raw_affiliation_string":"Indian Institute of Technology Madras, Chennai, India","institution_ids":["https://openalex.org/I24676775"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5070515834","display_name":"R. Manimegalai","orcid":null},"institutions":[{"id":"https://openalex.org/I24676775","display_name":"Indian Institute of Technology Madras","ror":"https://ror.org/03v0r5n49","country_code":"IN","type":"facility","lineage":["https://openalex.org/I24676775"]}],"countries":["IN"],"is_corresponding":false,"raw_author_name":"R. Manimegalai","raw_affiliation_strings":["Indian Institute of Technology Madras, Chennai, India"],"affiliations":[{"raw_affiliation_string":"Indian Institute of Technology Madras, Chennai, India","institution_ids":["https://openalex.org/I24676775"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5046715331","display_name":"V. Kamakoti","orcid":null},"institutions":[{"id":"https://openalex.org/I24676775","display_name":"Indian Institute of Technology Madras","ror":"https://ror.org/03v0r5n49","country_code":"IN","type":"facility","lineage":["https://openalex.org/I24676775"]}],"countries":["IN"],"is_corresponding":false,"raw_author_name":"V. Kamakoti","raw_affiliation_strings":["Indian Institute of Technology Madras, Chennai, India"],"affiliations":[{"raw_affiliation_string":"Indian Institute of Technology Madras, Chennai, India","institution_ids":["https://openalex.org/I24676775"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":4,"corresponding_author_ids":["https://openalex.org/A5001436195"],"corresponding_institution_ids":["https://openalex.org/I24676775"],"apc_list":null,"apc_paid":null,"fwci":0.0,"has_fulltext":false,"cited_by_count":0,"citation_normalized_percentile":{"value":0.44123692,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":null,"biblio":{"volume":null,"issue":null,"first_page":"152","last_page":"159"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T11522","display_name":"VLSI and FPGA Design Techniques","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T11522","display_name":"VLSI and FPGA Design Techniques","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10904","display_name":"Embedded Systems Design Techniques","score":0.9993000030517578,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11032","display_name":"VLSI and Analog Circuit Testing","score":0.9991999864578247,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/benchmark","display_name":"Benchmark (surveying)","score":0.8019666075706482},{"id":"https://openalex.org/keywords/field-programmable-gate-array","display_name":"Field-programmable gate array","score":0.7719998359680176},{"id":"https://openalex.org/keywords/minification","display_name":"Minification","score":0.7535794973373413},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.7045146226882935},{"id":"https://openalex.org/keywords/reduction","display_name":"Reduction (mathematics)","score":0.7036473155021667},{"id":"https://openalex.org/keywords/electronic-circuit","display_name":"Electronic circuit","score":0.5671091675758362},{"id":"https://openalex.org/keywords/parallel-computing","display_name":"Parallel computing","score":0.5413321256637573},{"id":"https://openalex.org/keywords/algorithm","display_name":"Algorithm","score":0.4930054843425751},{"id":"https://openalex.org/keywords/computer-engineering","display_name":"Computer engineering","score":0.3980119824409485},{"id":"https://openalex.org/keywords/computer-hardware","display_name":"Computer hardware","score":0.3119581937789917},{"id":"https://openalex.org/keywords/mathematics","display_name":"Mathematics","score":0.15466853976249695},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.13462024927139282},{"id":"https://openalex.org/keywords/electrical-engineering","display_name":"Electrical engineering","score":0.06626659631729126}],"concepts":[{"id":"https://openalex.org/C185798385","wikidata":"https://www.wikidata.org/wiki/Q1161707","display_name":"Benchmark (surveying)","level":2,"score":0.8019666075706482},{"id":"https://openalex.org/C42935608","wikidata":"https://www.wikidata.org/wiki/Q190411","display_name":"Field-programmable gate array","level":2,"score":0.7719998359680176},{"id":"https://openalex.org/C147764199","wikidata":"https://www.wikidata.org/wiki/Q6865248","display_name":"Minification","level":2,"score":0.7535794973373413},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.7045146226882935},{"id":"https://openalex.org/C111335779","wikidata":"https://www.wikidata.org/wiki/Q3454686","display_name":"Reduction (mathematics)","level":2,"score":0.7036473155021667},{"id":"https://openalex.org/C134146338","wikidata":"https://www.wikidata.org/wiki/Q1815901","display_name":"Electronic circuit","level":2,"score":0.5671091675758362},{"id":"https://openalex.org/C173608175","wikidata":"https://www.wikidata.org/wiki/Q232661","display_name":"Parallel computing","level":1,"score":0.5413321256637573},{"id":"https://openalex.org/C11413529","wikidata":"https://www.wikidata.org/wiki/Q8366","display_name":"Algorithm","level":1,"score":0.4930054843425751},{"id":"https://openalex.org/C113775141","wikidata":"https://www.wikidata.org/wiki/Q428691","display_name":"Computer engineering","level":1,"score":0.3980119824409485},{"id":"https://openalex.org/C9390403","wikidata":"https://www.wikidata.org/wiki/Q3966","display_name":"Computer hardware","level":1,"score":0.3119581937789917},{"id":"https://openalex.org/C33923547","wikidata":"https://www.wikidata.org/wiki/Q395","display_name":"Mathematics","level":0,"score":0.15466853976249695},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.13462024927139282},{"id":"https://openalex.org/C119599485","wikidata":"https://www.wikidata.org/wiki/Q43035","display_name":"Electrical engineering","level":1,"score":0.06626659631729126},{"id":"https://openalex.org/C2524010","wikidata":"https://www.wikidata.org/wiki/Q8087","display_name":"Geometry","level":1,"score":0.0},{"id":"https://openalex.org/C13280743","wikidata":"https://www.wikidata.org/wiki/Q131089","display_name":"Geodesy","level":1,"score":0.0},{"id":"https://openalex.org/C205649164","wikidata":"https://www.wikidata.org/wiki/Q1071","display_name":"Geography","level":0,"score":0.0},{"id":"https://openalex.org/C199360897","wikidata":"https://www.wikidata.org/wiki/Q9143","display_name":"Programming language","level":1,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/ipdps.2004.1303140","is_oa":false,"landing_page_url":"https://doi.org/10.1109/ipdps.2004.1303140","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"18th International Parallel and Distributed Processing Symposium, 2004. Proceedings.","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[{"score":0.6800000071525574,"id":"https://metadata.un.org/sdg/7","display_name":"Affordable and clean energy"}],"awards":[],"funders":[],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":10,"referenced_works":["https://openalex.org/W1969802502","https://openalex.org/W1978998136","https://openalex.org/W1985856707","https://openalex.org/W2108539060","https://openalex.org/W2115047803","https://openalex.org/W2124456496","https://openalex.org/W2144736151","https://openalex.org/W2161582063","https://openalex.org/W4234601000","https://openalex.org/W4252590738"],"related_works":["https://openalex.org/W2378211422","https://openalex.org/W4321353415","https://openalex.org/W2745001401","https://openalex.org/W2130974462","https://openalex.org/W2028665553","https://openalex.org/W2086519370","https://openalex.org/W4246352526","https://openalex.org/W4400235630","https://openalex.org/W2048582679","https://openalex.org/W2782226720"],"abstract_inverted_index":{"Summary":[0],"form":[1],"only":[2],"given.":[3],"Modern":[4],"day":[5],"field":[6],"programmable":[7],"gate":[8],"arrays":[9],"(FPGA)":[10],"include":[11],"in":[12,83,121,133],"addition":[13],"to":[14,24,26,40,55,64,116,118],"look-up":[15,62],"tables,":[16],"reasonably":[17],"big":[18],"configurable":[19],"embedded":[20],"memory":[21,29],"blocks":[22],"(EMB)":[23],"cater":[25],"the":[27,45,70,76,86,126],"on-chip":[28],"requirements":[30],"of":[31,44,69,85,88],"systems/applications":[32],"mapped":[33],"on":[34,39,111],"them.":[35],"While":[36],"mapping":[37,98],"applications":[38],"such":[41,57],"FPGAs,":[42],"some":[43],"EMBs":[46,59],"may":[47],"be":[48],"left":[49],"unused.":[50],"We":[51],"present":[52],"a":[53],"methodology":[54],"utilize":[56],"unused":[58],"as":[60,75],"large":[61],"tables":[63],"map":[65],"multioutput":[66],"combinational":[67],"subcircuits":[68],"application,":[71],"with":[72,80,125,130],"depth":[73,122],"minimization":[74,82,92],"main":[77],"objective":[78],"along":[79,129],"area":[81],"terms":[84],"number":[87],"LUTs":[89],"used.":[90],"Depth":[91],"is":[93],"an":[94],"important":[95],"goal":[96],"while":[97],"performance":[99],"driven":[100],"circuits.":[101],"Experimental":[102],"results":[103],"show":[104],"that":[105],"our":[106],"proposed":[107],"methodology,":[108],"when":[109,123],"employed":[110],"popular":[112],"benchmark":[113],"circuits,":[114],"leads":[115],"up":[117],"14%":[119],"reduction":[120,132],"compared":[124],"DAG-map":[127],"algorithm,":[128],"comparable":[131],"area.":[134]},"counts_by_year":[],"updated_date":"2025-11-06T03:46:38.306776","created_date":"2025-10-10T00:00:00"}
