{"id":"https://openalex.org/W1939615570","doi":"https://doi.org/10.1109/ipdps.2003.1213334","title":"Reconfigurable processor architectures for mobile phones","display_name":"Reconfigurable processor architectures for mobile phones","publication_year":2004,"publication_date":"2004-03-22","ids":{"openalex":"https://openalex.org/W1939615570","doi":"https://doi.org/10.1109/ipdps.2003.1213334","mag":"1939615570"},"language":"en","primary_location":{"id":"doi:10.1109/ipdps.2003.1213334","is_oa":false,"landing_page_url":"https://doi.org/10.1109/ipdps.2003.1213334","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Proceedings International Parallel and Distributed Processing Symposium","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5062770961","display_name":"M. Vorbach","orcid":null},"institutions":[],"countries":[],"is_corresponding":false,"raw_author_name":"M. Vorbach","raw_affiliation_strings":["PACT XPP Technologies AG, Munich, Germany"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"PACT XPP Technologies AG, Munich, Germany","institution_ids":[]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5108383415","display_name":"Ralf Becker","orcid":null},"institutions":[{"id":"https://openalex.org/I4210088543","display_name":"Institut f\u00fcr Informationsverarbeitung","ror":"https://ror.org/0047j9t38","country_code":"DE","type":"facility","lineage":["https://openalex.org/I4210088543"]}],"countries":["DE"],"is_corresponding":false,"raw_author_name":"R. Becker","raw_affiliation_strings":["Institut fuer Technik der Informationsverarbeitung, Universitaet Karlsruhe, Karlsruhe, Germany"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Institut fuer Technik der Informationsverarbeitung, Universitaet Karlsruhe, Karlsruhe, Germany","institution_ids":["https://openalex.org/I4210088543"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":2,"corresponding_author_ids":[],"corresponding_institution_ids":[],"apc_list":null,"apc_paid":null,"fwci":3.7101,"has_fulltext":false,"cited_by_count":41,"citation_normalized_percentile":{"value":0.92574499,"is_in_top_1_percent":false,"is_in_top_10_percent":true},"cited_by_percentile_year":{"min":89,"max":98},"biblio":{"volume":null,"issue":null,"first_page":"6","last_page":"6"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10904","display_name":"Embedded Systems Design Techniques","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10904","display_name":"Embedded Systems Design Techniques","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10829","display_name":"Interconnection Networks and Systems","score":0.9990000128746033,"subfield":{"id":"https://openalex.org/subfields/1705","display_name":"Computer Networks and Communications"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10054","display_name":"Parallel Computing and Optimization Techniques","score":0.9986000061035156,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/datapath","display_name":"Datapath","score":0.8855066299438477},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.7795895338058472},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.602191150188446},{"id":"https://openalex.org/keywords/computer-architecture","display_name":"Computer architecture","score":0.5783981680870056},{"id":"https://openalex.org/keywords/field-programmable-gate-array","display_name":"Field-programmable gate array","score":0.5481522083282471},{"id":"https://openalex.org/keywords/system-on-a-chip","display_name":"System on a chip","score":0.42963290214538574},{"id":"https://openalex.org/keywords/architecture","display_name":"Architecture","score":0.41293883323669434},{"id":"https://openalex.org/keywords/computer-hardware","display_name":"Computer hardware","score":0.37514182925224304}],"concepts":[{"id":"https://openalex.org/C2781198647","wikidata":"https://www.wikidata.org/wiki/Q1633673","display_name":"Datapath","level":2,"score":0.8855066299438477},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.7795895338058472},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.602191150188446},{"id":"https://openalex.org/C118524514","wikidata":"https://www.wikidata.org/wiki/Q173212","display_name":"Computer architecture","level":1,"score":0.5783981680870056},{"id":"https://openalex.org/C42935608","wikidata":"https://www.wikidata.org/wiki/Q190411","display_name":"Field-programmable gate array","level":2,"score":0.5481522083282471},{"id":"https://openalex.org/C118021083","wikidata":"https://www.wikidata.org/wiki/Q610398","display_name":"System on a chip","level":2,"score":0.42963290214538574},{"id":"https://openalex.org/C123657996","wikidata":"https://www.wikidata.org/wiki/Q12271","display_name":"Architecture","level":2,"score":0.41293883323669434},{"id":"https://openalex.org/C9390403","wikidata":"https://www.wikidata.org/wiki/Q3966","display_name":"Computer hardware","level":1,"score":0.37514182925224304},{"id":"https://openalex.org/C142362112","wikidata":"https://www.wikidata.org/wiki/Q735","display_name":"Art","level":0,"score":0.0},{"id":"https://openalex.org/C153349607","wikidata":"https://www.wikidata.org/wiki/Q36649","display_name":"Visual arts","level":1,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/ipdps.2003.1213334","is_oa":false,"landing_page_url":"https://doi.org/10.1109/ipdps.2003.1213334","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Proceedings International Parallel and Distributed Processing Symposium","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[],"awards":[],"funders":[],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":14,"referenced_works":["https://openalex.org/W1649101858","https://openalex.org/W1837279029","https://openalex.org/W2083868341","https://openalex.org/W2112786708","https://openalex.org/W2117099910","https://openalex.org/W2127430515","https://openalex.org/W2137570657","https://openalex.org/W2346756768","https://openalex.org/W4234479839","https://openalex.org/W4243165422","https://openalex.org/W4254021074","https://openalex.org/W6638834831","https://openalex.org/W6676638905","https://openalex.org/W6704836821"],"related_works":["https://openalex.org/W1580556151","https://openalex.org/W2144463068","https://openalex.org/W2185915791","https://openalex.org/W2129565950","https://openalex.org/W2120705320","https://openalex.org/W37969803","https://openalex.org/W2158030625","https://openalex.org/W2169479409","https://openalex.org/W1996820488","https://openalex.org/W4302889242"],"abstract_inverted_index":{"This":[0],"paper":[1,53],"describes":[2],"a":[3,18],"new":[4],"dynamically":[5],"configurable":[6],"system-on-chip":[7],"(CSoC)":[8],"concept":[9],"and":[10,28,40,66],"integration,":[11],"consisting":[12],"of":[13,57],"an":[14,55],"ARM7":[15],"EJS":[16],"processor-core,":[17],"coarse-grain":[19],"4/spl":[20],"times/4":[21],"XPP-array":[22],"from":[23],"PACT":[24],"XPP":[25],"Technologies":[26],"AG,":[27],"application-tailored":[29],"global/local":[30],"memory":[31],"topology":[32],"with":[33],"efficient":[34],"Amba-based":[35],"communication":[36,49],"interfaces.":[37],"The":[38,52],"system":[39,60],"introduced":[41],"CSoC":[42],"architecture":[43],"is":[44],"optimized":[45],"for":[46],"the":[47,58,62],"mobile":[48],"algorithm":[50],"scenario.":[51],"gives":[54],"overview":[56],"overall":[59],"concept,":[61],"hardware":[63],"datapath":[64],"structures":[65],"their":[67],"integration":[68],"as":[69,71],"well":[70],"discussing":[72],"some":[73],"selected":[74],"application":[75],"implementation":[76],"results":[77],"within":[78],"this":[79],"target":[80],"area.":[81]},"counts_by_year":[{"year":2020,"cited_by_count":1},{"year":2017,"cited_by_count":1},{"year":2015,"cited_by_count":1},{"year":2014,"cited_by_count":4},{"year":2013,"cited_by_count":3},{"year":2012,"cited_by_count":1}],"updated_date":"2026-06-11T09:08:48.828518","created_date":"2025-10-10T00:00:00"}
