{"id":"https://openalex.org/W1544468925","doi":"https://doi.org/10.1109/ijcnn.2005.1556379","title":"A novel approach to reduce interconnect complexity in ANN hardware implementation","display_name":"A novel approach to reduce interconnect complexity in ANN hardware implementation","publication_year":2006,"publication_date":"2006-01-05","ids":{"openalex":"https://openalex.org/W1544468925","doi":"https://doi.org/10.1109/ijcnn.2005.1556379","mag":"1544468925"},"language":"en","primary_location":{"id":"doi:10.1109/ijcnn.2005.1556379","is_oa":false,"landing_page_url":"https://doi.org/10.1109/ijcnn.2005.1556379","pdf_url":null,"source":{"id":"https://openalex.org/S4363609022","display_name":"Proceedings. 2005 IEEE International Joint Conference on Neural Networks, 2005.","issn_l":null,"issn":null,"is_oa":false,"is_in_doaj":false,"is_core":false,"host_organization":null,"host_organization_name":null,"host_organization_lineage":[],"host_organization_lineage_names":[],"type":"conference"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Proceedings. 2005 IEEE International Joint Conference on Neural Networks, 2005.","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5063328352","display_name":"L. Brunelli","orcid":null},"institutions":[{"id":"https://openalex.org/I41455075","display_name":"Universidade Federal de Campina Grande","ror":"https://ror.org/00eftnx64","country_code":"BR","type":"education","lineage":["https://openalex.org/I41455075"]}],"countries":["BR"],"is_corresponding":true,"raw_author_name":"L. Brunelli","raw_affiliation_strings":["COPELE-Departamento de Engenharia Eletrica, Universidade Federal de Campina Grande, Campina Grande, Paraiba, Brazil","Departamento de Engenharia Eletrica, Univ. Fed. de Campina Grande, Brazil"],"affiliations":[{"raw_affiliation_string":"COPELE-Departamento de Engenharia Eletrica, Universidade Federal de Campina Grande, Campina Grande, Paraiba, Brazil","institution_ids":["https://openalex.org/I41455075"]},{"raw_affiliation_string":"Departamento de Engenharia Eletrica, Univ. Fed. de Campina Grande, Brazil","institution_ids":["https://openalex.org/I41455075"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5038249802","display_name":"Elmar U. K. Melcher","orcid":"https://orcid.org/0000-0003-0560-1131"},"institutions":[{"id":"https://openalex.org/I41455075","display_name":"Universidade Federal de Campina Grande","ror":"https://ror.org/00eftnx64","country_code":"BR","type":"education","lineage":["https://openalex.org/I41455075"]}],"countries":["BR"],"is_corresponding":false,"raw_author_name":"E.U.K. Melcher","raw_affiliation_strings":["COPELE-Departamento de Engenharia Eletrica, Universidade Federal de Campina Grande, Campina Grande, Paraiba, Brazil","Departamento de Engenharia Eletrica, Univ. Fed. de Campina Grande, Brazil"],"affiliations":[{"raw_affiliation_string":"COPELE-Departamento de Engenharia Eletrica, Universidade Federal de Campina Grande, Campina Grande, Paraiba, Brazil","institution_ids":["https://openalex.org/I41455075"]},{"raw_affiliation_string":"Departamento de Engenharia Eletrica, Univ. Fed. de Campina Grande, Brazil","institution_ids":["https://openalex.org/I41455075"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5081680179","display_name":"Alisson V. Brito","orcid":"https://orcid.org/0000-0001-5215-443X"},"institutions":[{"id":"https://openalex.org/I41455075","display_name":"Universidade Federal de Campina Grande","ror":"https://ror.org/00eftnx64","country_code":"BR","type":"education","lineage":["https://openalex.org/I41455075"]}],"countries":["BR"],"is_corresponding":false,"raw_author_name":"A.V. de Brito","raw_affiliation_strings":["COPELE-Departamento de Engenharia Eletrica, Universidade Federal de Campina Grande, Campina Grande, Paraiba, Brazil","Departamento de Engenharia Eletrica, Univ. Fed. de Campina Grande, Brazil"],"affiliations":[{"raw_affiliation_string":"COPELE-Departamento de Engenharia Eletrica, Universidade Federal de Campina Grande, Campina Grande, Paraiba, Brazil","institution_ids":["https://openalex.org/I41455075"]},{"raw_affiliation_string":"Departamento de Engenharia Eletrica, Univ. Fed. de Campina Grande, Brazil","institution_ids":["https://openalex.org/I41455075"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5062396226","display_name":"Raimundo C. S. Freire","orcid":"https://orcid.org/0000-0002-5395-7143"},"institutions":[{"id":"https://openalex.org/I41455075","display_name":"Universidade Federal de Campina Grande","ror":"https://ror.org/00eftnx64","country_code":"BR","type":"education","lineage":["https://openalex.org/I41455075"]}],"countries":["BR"],"is_corresponding":false,"raw_author_name":"R.C.S. Freire","raw_affiliation_strings":["COPELE-Departamento de Engenharia El\u00e9trica, Universidade Federal de Campina Grande, Campina Grande, Paraiba, Brazil","Departamento de Engenharia Eletrica, Univ. Fed. de Campina Grande, Brazil"],"affiliations":[{"raw_affiliation_string":"COPELE-Departamento de Engenharia El\u00e9trica, Universidade Federal de Campina Grande, Campina Grande, Paraiba, Brazil","institution_ids":["https://openalex.org/I41455075"]},{"raw_affiliation_string":"Departamento de Engenharia Eletrica, Univ. Fed. de Campina Grande, Brazil","institution_ids":["https://openalex.org/I41455075"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":4,"corresponding_author_ids":["https://openalex.org/A5063328352"],"corresponding_institution_ids":["https://openalex.org/I41455075"],"apc_list":null,"apc_paid":null,"fwci":1.0277,"has_fulltext":false,"cited_by_count":3,"citation_normalized_percentile":{"value":0.67973856,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":90,"max":94},"biblio":{"volume":"5","issue":null,"first_page":"2861","last_page":"2866"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10904","display_name":"Embedded Systems Design Techniques","score":0.9993000030517578,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10904","display_name":"Embedded Systems Design Techniques","score":0.9993000030517578,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10502","display_name":"Advanced Memory and Neural Computing","score":0.9980999827384949,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11032","display_name":"VLSI and Analog Circuit Testing","score":0.9973999857902527,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/interconnection","display_name":"Interconnection","score":0.8160721063613892},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.7961812019348145},{"id":"https://openalex.org/keywords/field-programmable-gate-array","display_name":"Field-programmable gate array","score":0.7703239321708679},{"id":"https://openalex.org/keywords/artificial-neural-network","display_name":"Artificial neural network","score":0.6780117750167847},{"id":"https://openalex.org/keywords/computation","display_name":"Computation","score":0.5969274640083313},{"id":"https://openalex.org/keywords/computational-complexity-theory","display_name":"Computational complexity theory","score":0.5812664031982422},{"id":"https://openalex.org/keywords/computer-architecture","display_name":"Computer architecture","score":0.4334872364997864},{"id":"https://openalex.org/keywords/distributed-computing","display_name":"Distributed computing","score":0.4246722459793091},{"id":"https://openalex.org/keywords/parallel-computing","display_name":"Parallel computing","score":0.3992076516151428},{"id":"https://openalex.org/keywords/computer-engineering","display_name":"Computer engineering","score":0.36394202709198},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.35720306634902954},{"id":"https://openalex.org/keywords/artificial-intelligence","display_name":"Artificial intelligence","score":0.2464522421360016},{"id":"https://openalex.org/keywords/algorithm","display_name":"Algorithm","score":0.1507934033870697},{"id":"https://openalex.org/keywords/computer-network","display_name":"Computer network","score":0.11027973890304565}],"concepts":[{"id":"https://openalex.org/C123745756","wikidata":"https://www.wikidata.org/wiki/Q1665949","display_name":"Interconnection","level":2,"score":0.8160721063613892},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.7961812019348145},{"id":"https://openalex.org/C42935608","wikidata":"https://www.wikidata.org/wiki/Q190411","display_name":"Field-programmable gate array","level":2,"score":0.7703239321708679},{"id":"https://openalex.org/C50644808","wikidata":"https://www.wikidata.org/wiki/Q192776","display_name":"Artificial neural network","level":2,"score":0.6780117750167847},{"id":"https://openalex.org/C45374587","wikidata":"https://www.wikidata.org/wiki/Q12525525","display_name":"Computation","level":2,"score":0.5969274640083313},{"id":"https://openalex.org/C179799912","wikidata":"https://www.wikidata.org/wiki/Q205084","display_name":"Computational complexity theory","level":2,"score":0.5812664031982422},{"id":"https://openalex.org/C118524514","wikidata":"https://www.wikidata.org/wiki/Q173212","display_name":"Computer architecture","level":1,"score":0.4334872364997864},{"id":"https://openalex.org/C120314980","wikidata":"https://www.wikidata.org/wiki/Q180634","display_name":"Distributed computing","level":1,"score":0.4246722459793091},{"id":"https://openalex.org/C173608175","wikidata":"https://www.wikidata.org/wiki/Q232661","display_name":"Parallel computing","level":1,"score":0.3992076516151428},{"id":"https://openalex.org/C113775141","wikidata":"https://www.wikidata.org/wiki/Q428691","display_name":"Computer engineering","level":1,"score":0.36394202709198},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.35720306634902954},{"id":"https://openalex.org/C154945302","wikidata":"https://www.wikidata.org/wiki/Q11660","display_name":"Artificial intelligence","level":1,"score":0.2464522421360016},{"id":"https://openalex.org/C11413529","wikidata":"https://www.wikidata.org/wiki/Q8366","display_name":"Algorithm","level":1,"score":0.1507934033870697},{"id":"https://openalex.org/C31258907","wikidata":"https://www.wikidata.org/wiki/Q1301371","display_name":"Computer network","level":1,"score":0.11027973890304565}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/ijcnn.2005.1556379","is_oa":false,"landing_page_url":"https://doi.org/10.1109/ijcnn.2005.1556379","pdf_url":null,"source":{"id":"https://openalex.org/S4363609022","display_name":"Proceedings. 2005 IEEE International Joint Conference on Neural Networks, 2005.","issn_l":null,"issn":null,"is_oa":false,"is_in_doaj":false,"is_core":false,"host_organization":null,"host_organization_name":null,"host_organization_lineage":[],"host_organization_lineage_names":[],"type":"conference"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Proceedings. 2005 IEEE International Joint Conference on Neural Networks, 2005.","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[],"awards":[],"funders":[],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":24,"referenced_works":["https://openalex.org/W1580574716","https://openalex.org/W1904242537","https://openalex.org/W1975051142","https://openalex.org/W1975085273","https://openalex.org/W1990163358","https://openalex.org/W1999183681","https://openalex.org/W2029850906","https://openalex.org/W2041731892","https://openalex.org/W2042276850","https://openalex.org/W2048241573","https://openalex.org/W2092306433","https://openalex.org/W2094118194","https://openalex.org/W2097235647","https://openalex.org/W2097451609","https://openalex.org/W2113648965","https://openalex.org/W2114767355","https://openalex.org/W2115250772","https://openalex.org/W2115294662","https://openalex.org/W2150405043","https://openalex.org/W2169333805","https://openalex.org/W2490905019","https://openalex.org/W4239654162","https://openalex.org/W6634799689","https://openalex.org/W6640443432"],"related_works":["https://openalex.org/W2111241003","https://openalex.org/W2155019192","https://openalex.org/W2014709025","https://openalex.org/W4200391368","https://openalex.org/W2210979487","https://openalex.org/W2074043759","https://openalex.org/W1967938402","https://openalex.org/W2386041993","https://openalex.org/W1608572506","https://openalex.org/W2160474882"],"abstract_inverted_index":{"Hardware":[0],"implementation":[1],"of":[2,17,57,62],"large":[3],"digital":[4],"artificial":[5,32],"neural":[6,18,33],"networks":[7],"is":[8,70,82],"limited":[9],"by":[10],"several":[11],"constraints,":[12],"such":[13],"as":[14],"the":[15,28,47,55,60,75],"complexity":[16,79],"interconnections.":[19],"This":[20],"paper":[21],"presents":[22],"a":[23,43],"novel":[24],"approach":[25],"to":[26,73],"solve":[27],"interconnection":[29,78],"problem":[30],"for":[31],"networks,":[34],"using":[35],"reconfigurable":[36],"computing":[37],"and":[38,77],"dynamically":[39],"reconfigured":[40],"FPGAs":[41],"in":[42],"new":[44],"computational":[45],"way:":[46],"execution":[48],"patterns":[49],"(EPs).":[50],"The":[51],"EPs":[52],"allow":[53],"reducing":[54],"influence":[56],"interconnections":[58],"through":[59],"removal":[61],"data":[63,68],"transport":[64,69],"via":[65],"busses.":[66],"Thus,":[67],"not":[71],"necessary":[72],"perform":[74],"computation":[76],"between":[80],"neurons":[81],"reduced.":[83]},"counts_by_year":[{"year":2017,"cited_by_count":1}],"updated_date":"2025-11-06T03:46:38.306776","created_date":"2025-10-10T00:00:00"}
