{"id":"https://openalex.org/W1618285867","doi":"https://doi.org/10.1109/icvd.2000.812600","title":"Interconnect statistical modeling, structures and measurement methodology","display_name":"Interconnect statistical modeling, structures and measurement methodology","publication_year":2002,"publication_date":"2002-11-07","ids":{"openalex":"https://openalex.org/W1618285867","doi":"https://doi.org/10.1109/icvd.2000.812600","mag":"1618285867"},"language":"en","primary_location":{"id":"doi:10.1109/icvd.2000.812600","is_oa":false,"landing_page_url":"https://doi.org/10.1109/icvd.2000.812600","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"VLSI Design 2000. Wireless and Digital Imaging in the Millennium. Proceedings of 13th International Conference on VLSI Design","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5055874573","display_name":"A. Doganis","orcid":null},"institutions":[{"id":"https://openalex.org/I105695857","display_name":"Siemens (Hungary)","ror":"https://ror.org/01rk7mv85","country_code":"HU","type":"company","lineage":["https://openalex.org/I105695857","https://openalex.org/I1325886976"]},{"id":"https://openalex.org/I4210156212","display_name":"Mentor Technologies","ror":"https://ror.org/05vewsj04","country_code":"US","type":"other","lineage":["https://openalex.org/I4210156212"]}],"countries":["HU","US"],"is_corresponding":true,"raw_author_name":"A. Doganis","raw_affiliation_strings":["Mentor Graphics, San Jose, CA, USA","Mentor Graphics San Jose, CA, USA"],"affiliations":[{"raw_affiliation_string":"Mentor Graphics, San Jose, CA, USA","institution_ids":["https://openalex.org/I4210156212"]},{"raw_affiliation_string":"Mentor Graphics San Jose, CA, USA","institution_ids":["https://openalex.org/I105695857"]}]}],"institutions":[],"countries_distinct_count":2,"institutions_distinct_count":1,"corresponding_author_ids":["https://openalex.org/A5055874573"],"corresponding_institution_ids":["https://openalex.org/I105695857","https://openalex.org/I4210156212"],"apc_list":null,"apc_paid":null,"fwci":0.0,"has_fulltext":false,"cited_by_count":0,"citation_normalized_percentile":{"value":0.05163967,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":null,"biblio":{"volume":null,"issue":null,"first_page":"150","last_page":"150"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T11032","display_name":"VLSI and Analog Circuit Testing","score":0.9980999827384949,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T11032","display_name":"VLSI and Analog Circuit Testing","score":0.9980999827384949,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":0.9970999956130981,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11522","display_name":"VLSI and FPGA Design Techniques","score":0.995199978351593,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/interconnection","display_name":"Interconnection","score":0.7289584279060364},{"id":"https://openalex.org/keywords/solver","display_name":"Solver","score":0.6930689811706543},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.6061221361160278},{"id":"https://openalex.org/keywords/electronic-engineering","display_name":"Electronic engineering","score":0.6034695506095886},{"id":"https://openalex.org/keywords/scalability","display_name":"Scalability","score":0.5765131115913391},{"id":"https://openalex.org/keywords/parasitic-extraction","display_name":"Parasitic extraction","score":0.5360726714134216},{"id":"https://openalex.org/keywords/calibration","display_name":"Calibration","score":0.5111251473426819},{"id":"https://openalex.org/keywords/routing","display_name":"Routing (electronic design automation)","score":0.47479313611984253},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.23620536923408508}],"concepts":[{"id":"https://openalex.org/C123745756","wikidata":"https://www.wikidata.org/wiki/Q1665949","display_name":"Interconnection","level":2,"score":0.7289584279060364},{"id":"https://openalex.org/C2778770139","wikidata":"https://www.wikidata.org/wiki/Q1966904","display_name":"Solver","level":2,"score":0.6930689811706543},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.6061221361160278},{"id":"https://openalex.org/C24326235","wikidata":"https://www.wikidata.org/wiki/Q126095","display_name":"Electronic engineering","level":1,"score":0.6034695506095886},{"id":"https://openalex.org/C48044578","wikidata":"https://www.wikidata.org/wiki/Q727490","display_name":"Scalability","level":2,"score":0.5765131115913391},{"id":"https://openalex.org/C159818811","wikidata":"https://www.wikidata.org/wiki/Q7135947","display_name":"Parasitic extraction","level":2,"score":0.5360726714134216},{"id":"https://openalex.org/C165838908","wikidata":"https://www.wikidata.org/wiki/Q736777","display_name":"Calibration","level":2,"score":0.5111251473426819},{"id":"https://openalex.org/C74172769","wikidata":"https://www.wikidata.org/wiki/Q1446839","display_name":"Routing (electronic design automation)","level":2,"score":0.47479313611984253},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.23620536923408508},{"id":"https://openalex.org/C33923547","wikidata":"https://www.wikidata.org/wiki/Q395","display_name":"Mathematics","level":0,"score":0.0},{"id":"https://openalex.org/C199360897","wikidata":"https://www.wikidata.org/wiki/Q9143","display_name":"Programming language","level":1,"score":0.0},{"id":"https://openalex.org/C77088390","wikidata":"https://www.wikidata.org/wiki/Q8513","display_name":"Database","level":1,"score":0.0},{"id":"https://openalex.org/C31258907","wikidata":"https://www.wikidata.org/wiki/Q1301371","display_name":"Computer network","level":1,"score":0.0},{"id":"https://openalex.org/C105795698","wikidata":"https://www.wikidata.org/wiki/Q12483","display_name":"Statistics","level":1,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/icvd.2000.812600","is_oa":false,"landing_page_url":"https://doi.org/10.1109/icvd.2000.812600","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"VLSI Design 2000. Wireless and Digital Imaging in the Millennium. Proceedings of 13th International Conference on VLSI Design","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[],"awards":[],"funders":[],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":0,"referenced_works":[],"related_works":["https://openalex.org/W1905216755","https://openalex.org/W2104218257","https://openalex.org/W2117417104","https://openalex.org/W2534619547","https://openalex.org/W1923048618","https://openalex.org/W1990010037","https://openalex.org/W2198432996","https://openalex.org/W4255141013","https://openalex.org/W2889526943","https://openalex.org/W2076658455"],"abstract_inverted_index":{"Today,":[0],"ICs":[1],"are":[2,74,143,151,179,233],"fabricated":[3],"with":[4,94,166],"increasingly":[5],"more":[6,12],"metal":[7],"layers":[8],"as":[9,11,126,192,194,247],"well":[10,193],"routing":[13],"on":[14],"each":[15],"layer.":[16],"Interconnects":[17],"have":[18],"become":[19],"the":[20,38,41,56,95,99,135,156,186,189,195,198,207,253,276,280],"most":[21],"crucial":[22],"factor":[23],"of":[24,43,55,89,105,114,188,197],"signal":[25],"delays,":[26],"especially,":[27],"in":[28,164,183,251,275],"deep":[29,32],"and":[30,46,61,67,79,98,117,147,153,212,241,261,269,282,287],"very":[31],"submicron":[33],"designs.":[34],"To":[35],"accurately":[36],"predict":[37,279],"circuit":[39,57,213,254],"performance,":[40,60],"need":[42],"accurate,":[44,145],"fast,":[45],"scalable":[47],"interconnect":[48,66,90,118,138,199,223],"models":[49,142,217,224],"is":[50,203],"necessary":[51],"at":[52,76],"all":[53],"stages":[54],"analysis.":[58],"High":[59],"accurate":[62],"silicon":[63],"calibration":[64,113,187],"for":[65,112,155,225,235,243,284],"active":[68],"devices":[69],"using":[70,206],"specialized":[71,176],"test":[72,91,168,177],"structures":[73,92,108,124,178],"essential":[75],"0.25":[77],"micron":[78,263],"below.":[80],"In":[81],"this":[82],"work,":[83],"we":[84],"introduce":[85],"a":[86,248,267],"minimal":[87],"set":[88],"along":[93],"measurement":[96],"scheme":[97],"associated":[100],"extraction":[101,119],"methods.":[102],"On-chip":[103],"measurements":[104,257],"such":[106,125],"simple":[107],"will":[109,132,245,265],"be":[110],"used":[111],"field":[115,161,190],"solvers":[116],"tools.":[120],"Measurements":[121],"from":[122,175,258],"complex":[123],"clock":[127],"nets,":[128],"I/O's,":[129],"standard":[130],"cells,":[131],"farther":[133],"refine":[134],"generated":[136],"parasitic":[137],"models.":[139,201],"Those":[140],"empirical":[141],"simple,":[144],"compact":[146,200],"process":[148,159,172],"independent.":[149],"They":[150],"calibrated":[152],"optimized":[154],"particular":[157],"location":[158],"via":[160],"solver":[162,191],"simulations":[163],"connection":[165],"on-chip":[167],"structure":[169],"measurements.":[170],"Additionally,":[171],"variations":[173],"measured":[174],"taken":[180],"into":[181],"account":[182],"both":[184],"during":[185],"generation":[196],"This":[202],"achieved":[204],"by":[205],"principal":[208],"component":[209],"analysis":[210,231],"(PCA)":[211],"performance":[214,270,283],"response":[215],"surface":[216,271],"(RSM)":[218],"to":[219],"derive":[220],"statistically":[221],"meaningful":[222],"\"corner\"":[226],"or":[227],"\"statistical":[228],"worst":[229],"case\"":[230],"which":[232,273],"appropriate":[234],"xCalibre.":[236],"Yield":[237],"maximization,":[238],"design":[239,242],"centering":[240],"interconnectivity":[244],"follow":[246],"natural":[249],"step":[250],"improving":[252],"performance.":[255],"Furthermore,":[256],"0.25,":[259],"0.18,":[260],"0.15":[262],"technologies,":[264],"create":[266],"delay,":[268],"model":[272],"will,":[274],"first":[277],"order":[278],"delays":[281],"0.12":[285],"designs":[286],"beyond.":[288]},"counts_by_year":[],"updated_date":"2025-11-06T03:46:38.306776","created_date":"2025-10-10T00:00:00"}
