{"id":"https://openalex.org/W2118311746","doi":"https://doi.org/10.1109/icvd.1992.658015","title":"Functional Test Generation for Sequential Circuits","display_name":"Functional Test Generation for Sequential Circuits","publication_year":2005,"publication_date":"2005-08-24","ids":{"openalex":"https://openalex.org/W2118311746","doi":"https://doi.org/10.1109/icvd.1992.658015","mag":"2118311746"},"language":"en","primary_location":{"id":"doi:10.1109/icvd.1992.658015","is_oa":false,"landing_page_url":"https://doi.org/10.1109/icvd.1992.658015","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"The Fifth International Conference on VLSI Design","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5111912813","display_name":"J. Jacob","orcid":null},"institutions":[{"id":"https://openalex.org/I59270414","display_name":"Indian Institute of Science Bangalore","ror":"https://ror.org/04dese585","country_code":"IN","type":"education","lineage":["https://openalex.org/I59270414"]}],"countries":["IN"],"is_corresponding":false,"raw_author_name":"J. Jacob","raw_affiliation_strings":["Department of Electrical Communication Eng, Indian Institute of Science, Bangalore, Karnataka, India"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Department of Electrical Communication Eng, Indian Institute of Science, Bangalore, Karnataka, India","institution_ids":["https://openalex.org/I59270414"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5084081268","display_name":"Vishwani D. Agrawal","orcid":"https://orcid.org/0000-0002-7121-5979"},"institutions":[],"countries":[],"is_corresponding":false,"raw_author_name":"V.D. Agrawal","raw_affiliation_strings":["Computing Science Research Center, AT and T Bell Laboratories, Inc., Murray Hill, NJ, USA"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Computing Science Research Center, AT and T Bell Laboratories, Inc., Murray Hill, NJ, USA","institution_ids":[]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":2,"corresponding_author_ids":[],"corresponding_institution_ids":[],"apc_list":null,"apc_paid":null,"fwci":0.0,"has_fulltext":false,"cited_by_count":9,"citation_normalized_percentile":{"value":0.18800865,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":90,"max":94},"biblio":{"volume":"5","issue":null,"first_page":"17","last_page":"24"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T11032","display_name":"VLSI and Analog Circuit Testing","score":1.0,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T11032","display_name":"VLSI and Analog Circuit Testing","score":1.0,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11005","display_name":"Radiation Effects in Electronics","score":0.9995999932289124,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T14117","display_name":"Integrated Circuits and Semiconductor Failure Analysis","score":0.9991000294685364,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/combinational-logic","display_name":"Combinational logic","score":0.8570815324783325},{"id":"https://openalex.org/keywords/sequential-logic","display_name":"Sequential logic","score":0.6791183948516846},{"id":"https://openalex.org/keywords/automatic-test-pattern-generation","display_name":"Automatic test pattern generation","score":0.6541097164154053},{"id":"https://openalex.org/keywords/algorithm","display_name":"Algorithm","score":0.5910328030586243},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.5358520746231079},{"id":"https://openalex.org/keywords/sequence","display_name":"Sequence (biology)","score":0.5206565260887146},{"id":"https://openalex.org/keywords/testability","display_name":"Testability","score":0.47132208943367004},{"id":"https://openalex.org/keywords/benchmark","display_name":"Benchmark (surveying)","score":0.47043249011039734},{"id":"https://openalex.org/keywords/fault-coverage","display_name":"Fault coverage","score":0.4653158187866211},{"id":"https://openalex.org/keywords/logic-synthesis","display_name":"Logic synthesis","score":0.4562086760997772},{"id":"https://openalex.org/keywords/programmable-logic-device","display_name":"Programmable logic device","score":0.4525607228279114},{"id":"https://openalex.org/keywords/logic-gate","display_name":"Logic gate","score":0.435360848903656},{"id":"https://openalex.org/keywords/finite-state-machine","display_name":"Finite-state machine","score":0.43445122241973877},{"id":"https://openalex.org/keywords/stuck-at-fault","display_name":"Stuck-at fault","score":0.42978808283805847},{"id":"https://openalex.org/keywords/mathematics","display_name":"Mathematics","score":0.3227955102920532},{"id":"https://openalex.org/keywords/electronic-circuit","display_name":"Electronic circuit","score":0.27282261848449707},{"id":"https://openalex.org/keywords/fault-detection-and-isolation","display_name":"Fault detection and isolation","score":0.22318288683891296},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.14793509244918823},{"id":"https://openalex.org/keywords/computer-hardware","display_name":"Computer hardware","score":0.12168502807617188},{"id":"https://openalex.org/keywords/artificial-intelligence","display_name":"Artificial intelligence","score":0.08483937382698059}],"concepts":[{"id":"https://openalex.org/C81409106","wikidata":"https://www.wikidata.org/wiki/Q76505","display_name":"Combinational logic","level":3,"score":0.8570815324783325},{"id":"https://openalex.org/C187075797","wikidata":"https://www.wikidata.org/wiki/Q173245","display_name":"Sequential logic","level":3,"score":0.6791183948516846},{"id":"https://openalex.org/C17626397","wikidata":"https://www.wikidata.org/wiki/Q837455","display_name":"Automatic test pattern generation","level":3,"score":0.6541097164154053},{"id":"https://openalex.org/C11413529","wikidata":"https://www.wikidata.org/wiki/Q8366","display_name":"Algorithm","level":1,"score":0.5910328030586243},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.5358520746231079},{"id":"https://openalex.org/C2778112365","wikidata":"https://www.wikidata.org/wiki/Q3511065","display_name":"Sequence (biology)","level":2,"score":0.5206565260887146},{"id":"https://openalex.org/C51234621","wikidata":"https://www.wikidata.org/wiki/Q2149495","display_name":"Testability","level":2,"score":0.47132208943367004},{"id":"https://openalex.org/C185798385","wikidata":"https://www.wikidata.org/wiki/Q1161707","display_name":"Benchmark (surveying)","level":2,"score":0.47043249011039734},{"id":"https://openalex.org/C126953365","wikidata":"https://www.wikidata.org/wiki/Q5438152","display_name":"Fault coverage","level":3,"score":0.4653158187866211},{"id":"https://openalex.org/C157922185","wikidata":"https://www.wikidata.org/wiki/Q173198","display_name":"Logic synthesis","level":3,"score":0.4562086760997772},{"id":"https://openalex.org/C206274596","wikidata":"https://www.wikidata.org/wiki/Q1063837","display_name":"Programmable logic device","level":2,"score":0.4525607228279114},{"id":"https://openalex.org/C131017901","wikidata":"https://www.wikidata.org/wiki/Q170451","display_name":"Logic gate","level":2,"score":0.435360848903656},{"id":"https://openalex.org/C167822520","wikidata":"https://www.wikidata.org/wiki/Q176452","display_name":"Finite-state machine","level":2,"score":0.43445122241973877},{"id":"https://openalex.org/C13625343","wikidata":"https://www.wikidata.org/wiki/Q7627418","display_name":"Stuck-at fault","level":4,"score":0.42978808283805847},{"id":"https://openalex.org/C33923547","wikidata":"https://www.wikidata.org/wiki/Q395","display_name":"Mathematics","level":0,"score":0.3227955102920532},{"id":"https://openalex.org/C134146338","wikidata":"https://www.wikidata.org/wiki/Q1815901","display_name":"Electronic circuit","level":2,"score":0.27282261848449707},{"id":"https://openalex.org/C152745839","wikidata":"https://www.wikidata.org/wiki/Q5438153","display_name":"Fault detection and isolation","level":3,"score":0.22318288683891296},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.14793509244918823},{"id":"https://openalex.org/C9390403","wikidata":"https://www.wikidata.org/wiki/Q3966","display_name":"Computer hardware","level":1,"score":0.12168502807617188},{"id":"https://openalex.org/C154945302","wikidata":"https://www.wikidata.org/wiki/Q11660","display_name":"Artificial intelligence","level":1,"score":0.08483937382698059},{"id":"https://openalex.org/C13280743","wikidata":"https://www.wikidata.org/wiki/Q131089","display_name":"Geodesy","level":1,"score":0.0},{"id":"https://openalex.org/C86803240","wikidata":"https://www.wikidata.org/wiki/Q420","display_name":"Biology","level":0,"score":0.0},{"id":"https://openalex.org/C54355233","wikidata":"https://www.wikidata.org/wiki/Q7162","display_name":"Genetics","level":1,"score":0.0},{"id":"https://openalex.org/C105795698","wikidata":"https://www.wikidata.org/wiki/Q12483","display_name":"Statistics","level":1,"score":0.0},{"id":"https://openalex.org/C205649164","wikidata":"https://www.wikidata.org/wiki/Q1071","display_name":"Geography","level":0,"score":0.0},{"id":"https://openalex.org/C119599485","wikidata":"https://www.wikidata.org/wiki/Q43035","display_name":"Electrical engineering","level":1,"score":0.0},{"id":"https://openalex.org/C172707124","wikidata":"https://www.wikidata.org/wiki/Q423488","display_name":"Actuator","level":2,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/icvd.1992.658015","is_oa":false,"landing_page_url":"https://doi.org/10.1109/icvd.1992.658015","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"The Fifth International Conference on VLSI Design","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[],"awards":[],"funders":[],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":23,"referenced_works":["https://openalex.org/W1593401011","https://openalex.org/W1677852443","https://openalex.org/W1974372110","https://openalex.org/W1983881446","https://openalex.org/W1991643564","https://openalex.org/W2021489604","https://openalex.org/W2034570505","https://openalex.org/W2036887642","https://openalex.org/W2047307891","https://openalex.org/W2076273505","https://openalex.org/W2083807469","https://openalex.org/W2085966211","https://openalex.org/W2088013285","https://openalex.org/W2105761964","https://openalex.org/W2112206779","https://openalex.org/W2122837902","https://openalex.org/W2140824755","https://openalex.org/W2146816098","https://openalex.org/W2147833146","https://openalex.org/W2149107969","https://openalex.org/W2170668119","https://openalex.org/W4236231374","https://openalex.org/W4239107199"],"related_works":["https://openalex.org/W2169576796","https://openalex.org/W29481652","https://openalex.org/W4238178324","https://openalex.org/W4248668797","https://openalex.org/W2110968362","https://openalex.org/W2168652618","https://openalex.org/W3141297747","https://openalex.org/W1603944672","https://openalex.org/W2161696808","https://openalex.org/W2885828488"],"abstract_inverted_index":{"We":[0],"propose":[1],"a":[2,60,77,130,138,142,150],"method":[3,62],"of":[4,39,44,80,114,137],"generating":[5],"tests":[6,75,102],"for":[7,20,53,65,103,129,145],"finite":[8],"state":[9,139],"machines":[10],"(FSMs)":[11],"from":[12],"the":[13,33,40,45,92,104,115,125,146,162],"same":[14],"functional":[15],"description":[16,35],"that":[17,73,173],"is":[18,71,121,158],"used":[19],"logic":[21,49,67,117,148],"synthesis.":[22],"The":[23,154,166],"faults":[24,31,55,84],"are":[25,56],"modeled":[26],"as":[27,110],"growth":[28,131],"and":[29,90,149],"disappearance":[30,133],"in":[32,85,91],"cubical":[34],"(or":[36],"personality":[37,119],"matrix)":[38],"irredundant":[41,87],"combinational":[42,48,116,147],"part":[43],"FSM.":[46],"For":[47],"alone,":[50],"test":[51,128,143,164],"vectors":[52],"these":[54,74],"eficiently":[57],"derived":[58],"using":[59],"cube-based":[61,155],"previously":[63],"developed":[64],"programmable":[66],"arrays":[68],"(PLAs).":[69],"It":[70],"shown":[72],"provide":[76],"100%":[78,175],"coverage":[79,179],"single":[81],"stuck":[82,176],"type":[83,177],"any":[86],"twolevel":[88],"implementation":[89,94],"multi-level":[93],"obtained":[95,182],"through":[96],"testability":[97],"preserving":[98],"transformations.":[99],"To":[100],"derive":[101],"sequential":[105],"circuit,":[106],"we":[107],"represent":[108],"it":[109],"an":[111],"iterative":[112],"array":[113],"whose":[118],"matrix":[120],"modified":[122],"according":[123],"to":[124,160],"fault.":[126],"A":[127],"or":[132],"fault":[134,151,178],"now":[135],"consists":[136],"justification":[140],"sequence,":[141],"vector":[144],"propagation":[152],"sequence.":[153,165],"PLA":[156],"algorithm":[157],"extended":[159],"obtain":[161],"entire":[163],"results":[167],"on":[168],"synthesis":[169],"benchmark":[170],"circuits":[171],"show":[172],"almost":[174],"can":[180],"be":[181],"with":[183],"this":[184],"technique.":[185]},"counts_by_year":[{"year":2019,"cited_by_count":1}],"updated_date":"2026-06-11T09:08:48.828518","created_date":"2025-10-10T00:00:00"}
