{"id":"https://openalex.org/W2122337461","doi":"https://doi.org/10.1109/icpads.1996.517580","title":"Register renaming for x86 superscalar design","display_name":"Register renaming for x86 superscalar design","publication_year":2002,"publication_date":"2002-12-23","ids":{"openalex":"https://openalex.org/W2122337461","doi":"https://doi.org/10.1109/icpads.1996.517580","mag":"2122337461"},"language":"en","primary_location":{"id":"doi:10.1109/icpads.1996.517580","is_oa":false,"landing_page_url":"https://doi.org/10.1109/icpads.1996.517580","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Proceedings of 1996 International Conference on Parallel and Distributed Systems","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":null,"display_name":"Chang-Chung Liu","orcid":null},"institutions":[{"id":"https://openalex.org/I148366613","display_name":"National Yang Ming Chiao Tung University","ror":"https://ror.org/00se2k293","country_code":"TW","type":"education","lineage":["https://openalex.org/I148366613"]}],"countries":["TW"],"is_corresponding":false,"raw_author_name":"Chang-Chung Liu","raw_affiliation_strings":["Institute of Computer Science and Information Engineering, National Chiao Tung University, Hsinchu, Taiwan","Institute of Computer Science and Information Engineering, National Chiao-Tung University, Hsinchu, Taiwan"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Institute of Computer Science and Information Engineering, National Chiao Tung University, Hsinchu, Taiwan","institution_ids":["https://openalex.org/I148366613"]},{"raw_affiliation_string":"Institute of Computer Science and Information Engineering, National Chiao-Tung University, Hsinchu, Taiwan","institution_ids":["https://openalex.org/I148366613"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5042830813","display_name":"R-Ming Shiu","orcid":null},"institutions":[{"id":"https://openalex.org/I148366613","display_name":"National Yang Ming Chiao Tung University","ror":"https://ror.org/00se2k293","country_code":"TW","type":"education","lineage":["https://openalex.org/I148366613"]}],"countries":["TW"],"is_corresponding":false,"raw_author_name":"R-Ming Shiu","raw_affiliation_strings":["Institute of Computer Science and Information Engineering, National Chiao Tung University, Hsinchu, Taiwan","Institute of Computer Science and Information Engineering, National Chiao-Tung University, Hsinchu, Taiwan"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Institute of Computer Science and Information Engineering, National Chiao Tung University, Hsinchu, Taiwan","institution_ids":["https://openalex.org/I148366613"]},{"raw_affiliation_string":"Institute of Computer Science and Information Engineering, National Chiao-Tung University, Hsinchu, Taiwan","institution_ids":["https://openalex.org/I148366613"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5081637367","display_name":"Chung-Ping Chung","orcid":null},"institutions":[{"id":"https://openalex.org/I148366613","display_name":"National Yang Ming Chiao Tung University","ror":"https://ror.org/00se2k293","country_code":"TW","type":"education","lineage":["https://openalex.org/I148366613"]}],"countries":["TW"],"is_corresponding":false,"raw_author_name":"Chung-Ping Chung","raw_affiliation_strings":["Institute of Computer Science and Information Engineering, National Chiao Tung University, Hsinchu, Taiwan","Institute of Computer Science and Information Engineering, National Chiao-Tung University, Hsinchu, Taiwan"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Institute of Computer Science and Information Engineering, National Chiao Tung University, Hsinchu, Taiwan","institution_ids":["https://openalex.org/I148366613"]},{"raw_affiliation_string":"Institute of Computer Science and Information Engineering, National Chiao-Tung University, Hsinchu, Taiwan","institution_ids":["https://openalex.org/I148366613"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":3,"corresponding_author_ids":[],"corresponding_institution_ids":[],"apc_list":null,"apc_paid":null,"fwci":0.0,"has_fulltext":false,"cited_by_count":0,"citation_normalized_percentile":{"value":0.15639243,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":null,"biblio":{"volume":"9","issue":null,"first_page":"336","last_page":"343"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10054","display_name":"Parallel Computing and Optimization Techniques","score":1.0,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10054","display_name":"Parallel Computing and Optimization Techniques","score":1.0,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11181","display_name":"Advanced Data Storage Technologies","score":0.9972000122070312,"subfield":{"id":"https://openalex.org/subfields/1705","display_name":"Computer Networks and Communications"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10829","display_name":"Interconnection Networks and Systems","score":0.9918000102043152,"subfield":{"id":"https://openalex.org/subfields/1705","display_name":"Computer Networks and Communications"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/x86","display_name":"x86","score":0.8666908144950867},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.8650332689285278},{"id":"https://openalex.org/keywords/register-file","display_name":"Register file","score":0.7518309354782104},{"id":"https://openalex.org/keywords/register","display_name":"Register (sociolinguistics)","score":0.7215129137039185},{"id":"https://openalex.org/keywords/parallel-computing","display_name":"Parallel computing","score":0.7072038650512695},{"id":"https://openalex.org/keywords/register-allocation","display_name":"Register allocation","score":0.637098491191864},{"id":"https://openalex.org/keywords/processor-register","display_name":"Processor register","score":0.6365945339202881},{"id":"https://openalex.org/keywords/parallelism","display_name":"Parallelism (grammar)","score":0.5468688607215881},{"id":"https://openalex.org/keywords/scheme","display_name":"Scheme (mathematics)","score":0.5256905555725098},{"id":"https://openalex.org/keywords/superscalar","display_name":"Superscalar","score":0.4872678518295288},{"id":"https://openalex.org/keywords/instruction-level-parallelism","display_name":"Instruction-level parallelism","score":0.43043187260627747},{"id":"https://openalex.org/keywords/computer-architecture","display_name":"Computer architecture","score":0.3919210731983185},{"id":"https://openalex.org/keywords/computer-hardware","display_name":"Computer hardware","score":0.3439907431602478},{"id":"https://openalex.org/keywords/instruction-set","display_name":"Instruction set","score":0.27596890926361084},{"id":"https://openalex.org/keywords/operating-system","display_name":"Operating system","score":0.20953679084777832},{"id":"https://openalex.org/keywords/memory-address","display_name":"Memory address","score":0.1457417905330658},{"id":"https://openalex.org/keywords/software","display_name":"Software","score":0.09232142567634583},{"id":"https://openalex.org/keywords/semiconductor-memory","display_name":"Semiconductor memory","score":0.06023591756820679}],"concepts":[{"id":"https://openalex.org/C170723468","wikidata":"https://www.wikidata.org/wiki/Q182933","display_name":"x86","level":3,"score":0.8666908144950867},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.8650332689285278},{"id":"https://openalex.org/C117280010","wikidata":"https://www.wikidata.org/wiki/Q180944","display_name":"Register file","level":3,"score":0.7518309354782104},{"id":"https://openalex.org/C2779235478","wikidata":"https://www.wikidata.org/wiki/Q286576","display_name":"Register (sociolinguistics)","level":2,"score":0.7215129137039185},{"id":"https://openalex.org/C173608175","wikidata":"https://www.wikidata.org/wiki/Q232661","display_name":"Parallel computing","level":1,"score":0.7072038650512695},{"id":"https://openalex.org/C128916667","wikidata":"https://www.wikidata.org/wiki/Q1343660","display_name":"Register allocation","level":3,"score":0.637098491191864},{"id":"https://openalex.org/C2871975","wikidata":"https://www.wikidata.org/wiki/Q187466","display_name":"Processor register","level":4,"score":0.6365945339202881},{"id":"https://openalex.org/C2781172179","wikidata":"https://www.wikidata.org/wiki/Q853109","display_name":"Parallelism (grammar)","level":2,"score":0.5468688607215881},{"id":"https://openalex.org/C77618280","wikidata":"https://www.wikidata.org/wiki/Q1155772","display_name":"Scheme (mathematics)","level":2,"score":0.5256905555725098},{"id":"https://openalex.org/C147101560","wikidata":"https://www.wikidata.org/wiki/Q1045706","display_name":"Superscalar","level":2,"score":0.4872678518295288},{"id":"https://openalex.org/C140763907","wikidata":"https://www.wikidata.org/wiki/Q2714055","display_name":"Instruction-level parallelism","level":3,"score":0.43043187260627747},{"id":"https://openalex.org/C118524514","wikidata":"https://www.wikidata.org/wiki/Q173212","display_name":"Computer architecture","level":1,"score":0.3919210731983185},{"id":"https://openalex.org/C9390403","wikidata":"https://www.wikidata.org/wiki/Q3966","display_name":"Computer hardware","level":1,"score":0.3439907431602478},{"id":"https://openalex.org/C202491316","wikidata":"https://www.wikidata.org/wiki/Q272683","display_name":"Instruction set","level":2,"score":0.27596890926361084},{"id":"https://openalex.org/C111919701","wikidata":"https://www.wikidata.org/wiki/Q9135","display_name":"Operating system","level":1,"score":0.20953679084777832},{"id":"https://openalex.org/C153247305","wikidata":"https://www.wikidata.org/wiki/Q835713","display_name":"Memory address","level":3,"score":0.1457417905330658},{"id":"https://openalex.org/C2777904410","wikidata":"https://www.wikidata.org/wiki/Q7397","display_name":"Software","level":2,"score":0.09232142567634583},{"id":"https://openalex.org/C98986596","wikidata":"https://www.wikidata.org/wiki/Q1143031","display_name":"Semiconductor memory","level":2,"score":0.06023591756820679},{"id":"https://openalex.org/C169590947","wikidata":"https://www.wikidata.org/wiki/Q47506","display_name":"Compiler","level":2,"score":0.0},{"id":"https://openalex.org/C138885662","wikidata":"https://www.wikidata.org/wiki/Q5891","display_name":"Philosophy","level":0,"score":0.0},{"id":"https://openalex.org/C41895202","wikidata":"https://www.wikidata.org/wiki/Q8162","display_name":"Linguistics","level":1,"score":0.0},{"id":"https://openalex.org/C33923547","wikidata":"https://www.wikidata.org/wiki/Q395","display_name":"Mathematics","level":0,"score":0.0},{"id":"https://openalex.org/C134306372","wikidata":"https://www.wikidata.org/wiki/Q7754","display_name":"Mathematical analysis","level":1,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/icpads.1996.517580","is_oa":false,"landing_page_url":"https://doi.org/10.1109/icpads.1996.517580","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Proceedings of 1996 International Conference on Parallel and Distributed Systems","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[],"awards":[],"funders":[],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":15,"referenced_works":["https://openalex.org/W1499323045","https://openalex.org/W1555915743","https://openalex.org/W1987674899","https://openalex.org/W1990687271","https://openalex.org/W2031337049","https://openalex.org/W2090327856","https://openalex.org/W2100519017","https://openalex.org/W2107916517","https://openalex.org/W2119629105","https://openalex.org/W2147098645","https://openalex.org/W2167239776","https://openalex.org/W2170585292","https://openalex.org/W2293032043","https://openalex.org/W4244922846","https://openalex.org/W4248608571"],"related_works":["https://openalex.org/W2224192221","https://openalex.org/W1967889241","https://openalex.org/W2111377238","https://openalex.org/W2161297616","https://openalex.org/W3117494601","https://openalex.org/W4247209662","https://openalex.org/W2159389028","https://openalex.org/W2142891960","https://openalex.org/W4241759337","https://openalex.org/W4214554355"],"abstract_inverted_index":{"Register":[0],"renaming":[1,62],"eliminates":[2],"storage":[3],"conflicts":[4],"for":[5,69,76,92],"registers":[6,21],"to":[7,40,64],"allow":[8],"more":[9],"instruction":[10],"level":[11],"parallelism.":[12],"This":[13],"idea":[14],"requires":[15],"nontrivial":[16],"implementation,":[17],"however,":[18],"especially":[19],"when":[20],"are":[22,39],"accessible":[23],"with":[24],"different":[25],"fields":[26],"and":[27,47,73],"data":[28],"lengths.":[29],"As":[30],"a":[31,37,44,48],"result,":[32],"not":[33],"all":[34],"bits":[35],"in":[36],"register":[38,45,49,56],"be":[41,52],"updated":[42],"upon":[43],"write,":[46],"read":[50],"may":[51],"data-dependent":[53],"on":[54,86],"multiple":[55],"writes.":[57],"We":[58,81],"propose":[59],"two":[60,84],"hardware":[61,108],"schemes":[63,85],"solve":[65],"these":[66,83],"difficulties:":[67],"One":[68],"its":[70,77],"ultimate":[71],"performance,":[72],"the":[74,101,107,115,118],"other":[75],"desirable":[78],"cost/performance":[79],"ratio.":[80],"evaluate":[82],"an":[87],"aggressive":[88],"superscalar":[89],"machine":[90],"model":[91],"Intel":[93],"80/spl":[94],"times/86":[95],"architecture.":[96],"Simulation":[97],"results":[98],"show":[99],"that":[100],"second":[102],"scheme":[103],"can":[104],"effectively":[105],"reduce":[106],"cost":[109],"while":[110],"retaining":[111],"about":[112],"99%":[113],"of":[114,117],"performance":[116],"first.":[119]},"counts_by_year":[],"updated_date":"2026-06-11T09:08:48.828518","created_date":"2025-10-10T00:00:00"}
