{"id":"https://openalex.org/W2786006335","doi":"https://doi.org/10.1109/icm.2017.8268863","title":"A ultra high speed and configurable Inverse Discrete Wavelet Packet Transform architecture","display_name":"A ultra high speed and configurable Inverse Discrete Wavelet Packet Transform architecture","publication_year":2017,"publication_date":"2017-12-01","ids":{"openalex":"https://openalex.org/W2786006335","doi":"https://doi.org/10.1109/icm.2017.8268863","mag":"2786006335"},"language":"en","primary_location":{"id":"doi:10.1109/icm.2017.8268863","is_oa":false,"landing_page_url":"https://doi.org/10.1109/icm.2017.8268863","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2017 29th International Conference on Microelectronics (ICM)","raw_type":"proceedings-article"},"type":"preprint","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5023572913","display_name":"Mouhamad Chehaitly","orcid":null},"institutions":[{"id":"https://openalex.org/I1294671590","display_name":"Centre National de la Recherche Scientifique","ror":"https://ror.org/02feahw73","country_code":"FR","type":"government","lineage":["https://openalex.org/I1294671590"]},{"id":"https://openalex.org/I138816502","display_name":"Universit\u00e9 de Corse Pascal Paoli","ror":"https://ror.org/050ra0n32","country_code":"FR","type":"education","lineage":["https://openalex.org/I138816502"]},{"id":"https://openalex.org/I4387155471","display_name":"Laboratoire de G\u00e9nie Informatique, de Production et de Maintenance","ror":"https://ror.org/04xykxd72","country_code":null,"type":"facility","lineage":["https://openalex.org/I4210150706","https://openalex.org/I4387155471","https://openalex.org/I90183372","https://openalex.org/I90183372"]},{"id":"https://openalex.org/I90183372","display_name":"Universit\u00e9 de Lorraine","ror":"https://ror.org/04vfs2w97","country_code":"FR","type":"education","lineage":["https://openalex.org/I90183372"]}],"countries":["FR"],"is_corresponding":true,"raw_author_name":"Mouhamad Chehaitly","raw_affiliation_strings":["CNRS UMR SPE 6134, University of Corsica, Corte, France","LGIPM, Lorraine University, Metz, France"],"affiliations":[{"raw_affiliation_string":"CNRS UMR SPE 6134, University of Corsica, Corte, France","institution_ids":["https://openalex.org/I138816502","https://openalex.org/I1294671590"]},{"raw_affiliation_string":"LGIPM, Lorraine University, Metz, France","institution_ids":["https://openalex.org/I90183372","https://openalex.org/I4387155471"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5015679036","display_name":"Mohamed Tabaa","orcid":"https://orcid.org/0000-0003-3938-3566"},"institutions":[{"id":"https://openalex.org/I4210113095","display_name":"\u00c9cole Marocaine des Sciences de l'Ing\u00e9nieur","ror":"https://ror.org/01d1pbg09","country_code":"MA","type":"education","lineage":["https://openalex.org/I4210113095"]}],"countries":["MA"],"is_corresponding":false,"raw_author_name":"Mohamed Tabaa","raw_affiliation_strings":["EMSI, Multidisciplinary Research and Innovation Laboratory (LPRI), Casablanca, Morocco"],"affiliations":[{"raw_affiliation_string":"EMSI, Multidisciplinary Research and Innovation Laboratory (LPRI), Casablanca, Morocco","institution_ids":["https://openalex.org/I4210113095"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5112299208","display_name":"Fabrice Monteiro","orcid":null},"institutions":[{"id":"https://openalex.org/I4387155471","display_name":"Laboratoire de G\u00e9nie Informatique, de Production et de Maintenance","ror":"https://ror.org/04xykxd72","country_code":null,"type":"facility","lineage":["https://openalex.org/I4210150706","https://openalex.org/I4387155471","https://openalex.org/I90183372","https://openalex.org/I90183372"]},{"id":"https://openalex.org/I90183372","display_name":"Universit\u00e9 de Lorraine","ror":"https://ror.org/04vfs2w97","country_code":"FR","type":"education","lineage":["https://openalex.org/I90183372"]}],"countries":["FR"],"is_corresponding":false,"raw_author_name":"Fabrice Monteiro","raw_affiliation_strings":["LGIPM, Lorraine University, Metz, France"],"affiliations":[{"raw_affiliation_string":"LGIPM, Lorraine University, Metz, France","institution_ids":["https://openalex.org/I90183372","https://openalex.org/I4387155471"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5112557046","display_name":"Abbas Dandache","orcid":null},"institutions":[{"id":"https://openalex.org/I1294671590","display_name":"Centre National de la Recherche Scientifique","ror":"https://ror.org/02feahw73","country_code":"FR","type":"government","lineage":["https://openalex.org/I1294671590"]},{"id":"https://openalex.org/I138816502","display_name":"Universit\u00e9 de Corse Pascal Paoli","ror":"https://ror.org/050ra0n32","country_code":"FR","type":"education","lineage":["https://openalex.org/I138816502"]}],"countries":["FR"],"is_corresponding":false,"raw_author_name":"Abbas Dandache","raw_affiliation_strings":["CNRS UMR SPE 6134, University of Corsica, Corte, France"],"affiliations":[{"raw_affiliation_string":"CNRS UMR SPE 6134, University of Corsica, Corte, France","institution_ids":["https://openalex.org/I138816502","https://openalex.org/I1294671590"]}]}],"institutions":[],"countries_distinct_count":2,"institutions_distinct_count":4,"corresponding_author_ids":["https://openalex.org/A5023572913"],"corresponding_institution_ids":["https://openalex.org/I1294671590","https://openalex.org/I138816502","https://openalex.org/I4387155471","https://openalex.org/I90183372"],"apc_list":null,"apc_paid":null,"fwci":0.1853,"has_fulltext":false,"cited_by_count":3,"citation_normalized_percentile":{"value":0.60333029,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":89,"max":94},"biblio":{"volume":"315","issue":null,"first_page":"1","last_page":"4"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10901","display_name":"Advanced Data Compression Techniques","score":0.9995999932289124,"subfield":{"id":"https://openalex.org/subfields/1707","display_name":"Computer Vision and Pattern Recognition"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10901","display_name":"Advanced Data Compression Techniques","score":0.9995999932289124,"subfield":{"id":"https://openalex.org/subfields/1707","display_name":"Computer Vision and Pattern Recognition"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10688","display_name":"Image and Signal Denoising Methods","score":0.9994999766349792,"subfield":{"id":"https://openalex.org/subfields/1707","display_name":"Computer Vision and Pattern Recognition"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11034","display_name":"Digital Filter Design and Implementation","score":0.9979000091552734,"subfield":{"id":"https://openalex.org/subfields/1711","display_name":"Signal Processing"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.7076957821846008},{"id":"https://openalex.org/keywords/parallel-computing","display_name":"Parallel computing","score":0.604326605796814},{"id":"https://openalex.org/keywords/field-programmable-gate-array","display_name":"Field-programmable gate array","score":0.6031548380851746},{"id":"https://openalex.org/keywords/pipeline","display_name":"Pipeline (software)","score":0.5772926807403564},{"id":"https://openalex.org/keywords/vhdl","display_name":"VHDL","score":0.545943021774292},{"id":"https://openalex.org/keywords/algorithm","display_name":"Algorithm","score":0.3751230537891388},{"id":"https://openalex.org/keywords/computer-hardware","display_name":"Computer hardware","score":0.3222951591014862}],"concepts":[{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.7076957821846008},{"id":"https://openalex.org/C173608175","wikidata":"https://www.wikidata.org/wiki/Q232661","display_name":"Parallel computing","level":1,"score":0.604326605796814},{"id":"https://openalex.org/C42935608","wikidata":"https://www.wikidata.org/wiki/Q190411","display_name":"Field-programmable gate array","level":2,"score":0.6031548380851746},{"id":"https://openalex.org/C43521106","wikidata":"https://www.wikidata.org/wiki/Q2165493","display_name":"Pipeline (software)","level":2,"score":0.5772926807403564},{"id":"https://openalex.org/C36941000","wikidata":"https://www.wikidata.org/wiki/Q209455","display_name":"VHDL","level":3,"score":0.545943021774292},{"id":"https://openalex.org/C11413529","wikidata":"https://www.wikidata.org/wiki/Q8366","display_name":"Algorithm","level":1,"score":0.3751230537891388},{"id":"https://openalex.org/C9390403","wikidata":"https://www.wikidata.org/wiki/Q3966","display_name":"Computer hardware","level":1,"score":0.3222951591014862},{"id":"https://openalex.org/C199360897","wikidata":"https://www.wikidata.org/wiki/Q9143","display_name":"Programming language","level":1,"score":0.0}],"mesh":[],"locations_count":2,"locations":[{"id":"doi:10.1109/icm.2017.8268863","is_oa":false,"landing_page_url":"https://doi.org/10.1109/icm.2017.8268863","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2017 29th International Conference on Microelectronics (ICM)","raw_type":"proceedings-article"},{"id":"pmh:oai:HAL:hal-03293408v1","is_oa":false,"landing_page_url":"https://hal.univ-lorraine.fr/hal-03293408","pdf_url":null,"source":{"id":"https://openalex.org/S4306402512","display_name":"HAL (Le Centre pour la Communication Scientifique Directe)","issn_l":null,"issn":null,"is_oa":false,"is_in_doaj":false,"is_core":false,"host_organization":"https://openalex.org/I1294671590","host_organization_name":"Centre National de la Recherche Scientifique","host_organization_lineage":["https://openalex.org/I1294671590"],"host_organization_lineage_names":[],"type":"repository"},"license":null,"license_id":null,"version":"submittedVersion","is_accepted":false,"is_published":false,"raw_source_name":"2017 29th International Conference on Microelectronics (ICM), Dec 2017, Beirut, France. pp.1-4, ⟨10.1109/ICM.2017.8268863⟩","raw_type":"Conference papers"}],"best_oa_location":null,"sustainable_development_goals":[],"awards":[],"funders":[],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":10,"referenced_works":["https://openalex.org/W1601441232","https://openalex.org/W1848868226","https://openalex.org/W1980149518","https://openalex.org/W2008149160","https://openalex.org/W2033235405","https://openalex.org/W2106278621","https://openalex.org/W2132080924","https://openalex.org/W2143776884","https://openalex.org/W2156416765","https://openalex.org/W2157529380"],"related_works":["https://openalex.org/W3004362061","https://openalex.org/W4297665406","https://openalex.org/W2364622490","https://openalex.org/W2042515040","https://openalex.org/W2383986884","https://openalex.org/W2356141508","https://openalex.org/W1735031787","https://openalex.org/W2749962643","https://openalex.org/W2390807153","https://openalex.org/W2538906952"],"abstract_inverted_index":{"This":[0,48,112,199],"article":[1],"presents":[2],"a":[3,23,36,56,67,77],"new":[4],"pipeline-parallel":[5,44,86],"architecture":[6,42,45,49,113,200],"of":[7,43,46,59,85,93,100,106,121,132,137,153,178],"Inverse":[8],"Discrete":[9],"Wavelet":[10],"Packet":[11],"Transform":[12],"(IDWPT)":[13],"for":[14],"all":[15],"wavelet":[16],"family":[17],"implemented":[18],"in":[19,30,109,118,147,158,220],"FPGA":[20],"technology":[21],"using":[22,203],"parallel":[24,126],"direct":[25,79],"FIR":[26,80],"filter.":[27],"Our":[28],"aim":[29],"this":[31,94],"work":[32],"is":[33,96,114],"to":[34,150,174,192],"develop":[35],"generic":[37],"VHDL-RTL":[38],"model":[39,95],"and":[40,76,87,103,140,145,155,184,194,216],"configurable":[41],"IDWPT.":[47],"provide":[50],"ultra-high":[51],"speed":[52],"sample":[53],"processing":[54],"with":[55],"restricted":[57],"amount":[58],"used":[60],"hardware.":[61],"To":[62],"achieve":[63],"that,":[64],"we":[65],"propose":[66],"P-parallel":[68],"IDWPT":[69],"based":[70],"on":[71,197],"Mallat":[72],"binary":[73],"tree":[74,129,133,182],"algorithm":[75],"P-parallel/modified":[78],"filter":[81,142],"under":[82],"the":[83,97,110,125,128,135,138,141,151,161,170,181],"strategy":[84],"sharing":[88],"hardware":[89,105],"resource.":[90],"The":[91],"key":[92],"data":[98],"manage/interleaving":[99],"pipeline/P-parallel":[101],"concept":[102],"shared":[104],"different":[107],"level":[108,224],"transformation.":[111],"fully":[115],"configurable:":[116],"(i)":[117],"synthesis":[119],"according":[120,149],"various":[122],"parameters":[123],"like":[124],"degree,":[127],"depth":[130,183],"(number":[131],"levels),":[134],"order":[136,186],"filters":[139,162,185],"quantization":[143],"coefficient":[144],"(ii)":[146],"pro-synthesis":[148],"coefficients":[152,163],"low-pass":[154],"high-pass":[156],"filters,":[157],"other":[159],"words":[160],"can":[164],"be":[165],"loaded":[166],"after":[167],"synthesis.":[168],"Consequently,":[169],"simulation":[171],"results":[172],"accelerated":[173],"an":[175,210],"approximate":[176],"value":[177],"P*(Frequency).":[179],"Furthermore,":[180],"has":[187],"little":[188],"impact":[189],"(only":[190],"due":[191],"place":[193],"route":[195],"variations)":[196],"throughput.":[198],"was":[201,218],"synthesized":[202],"Altera":[204,211],"Quartus":[205],"prime":[206],"lite":[207],"edition":[208],"targeting":[209],"Cyclone":[212],"IV":[213],"-":[214],"(FPGA)":[215],"it":[217],"developed":[219],"VHDL":[221],"at":[222],"RTL":[223],"modeling.":[225]},"counts_by_year":[{"year":2022,"cited_by_count":1},{"year":2020,"cited_by_count":1},{"year":2018,"cited_by_count":1}],"updated_date":"2026-04-02T15:55:50.835912","created_date":"2025-10-10T00:00:00"}