{"id":"https://openalex.org/W2786769684","doi":"https://doi.org/10.1109/icm.2017.8268824","title":"A synthesizable serial link for point-to-point communication in SoC/NoC","display_name":"A synthesizable serial link for point-to-point communication in SoC/NoC","publication_year":2017,"publication_date":"2017-12-01","ids":{"openalex":"https://openalex.org/W2786769684","doi":"https://doi.org/10.1109/icm.2017.8268824","mag":"2786769684"},"language":"en","primary_location":{"id":"doi:10.1109/icm.2017.8268824","is_oa":false,"landing_page_url":"https://doi.org/10.1109/icm.2017.8268824","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2017 29th International Conference on Microelectronics (ICM)","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5051194064","display_name":"Maher Assaad","orcid":"https://orcid.org/0000-0002-1584-8747"},"institutions":[{"id":"https://openalex.org/I182000528","display_name":"Ajman University","ror":"https://ror.org/01j1rma10","country_code":"AE","type":"education","lineage":["https://openalex.org/I182000528"]}],"countries":["AE"],"is_corresponding":true,"raw_author_name":"Maher Assaad","raw_affiliation_strings":["Department of Electrical Engineering, Ajman University, Ajman, UAE"],"affiliations":[{"raw_affiliation_string":"Department of Electrical Engineering, Ajman University, Ajman, UAE","institution_ids":["https://openalex.org/I182000528"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5002290761","display_name":"Adnan Harb","orcid":"https://orcid.org/0000-0002-5032-4316"},"institutions":[{"id":"https://openalex.org/I4210104393","display_name":"International University of Beirut","ror":"https://ror.org/01fjkp854","country_code":"LB","type":"education","lineage":["https://openalex.org/I4210104393"]}],"countries":["LB"],"is_corresponding":false,"raw_author_name":"Adnan Harb","raw_affiliation_strings":["Department of Electrical and Electronics Engineering, International University of Beirut, Beirut, Lebanon"],"affiliations":[{"raw_affiliation_string":"Department of Electrical and Electronics Engineering, International University of Beirut, Beirut, Lebanon","institution_ids":["https://openalex.org/I4210104393"]}]}],"institutions":[],"countries_distinct_count":2,"institutions_distinct_count":2,"corresponding_author_ids":["https://openalex.org/A5051194064"],"corresponding_institution_ids":["https://openalex.org/I182000528"],"apc_list":null,"apc_paid":null,"fwci":0.0,"has_fulltext":false,"cited_by_count":0,"citation_normalized_percentile":{"value":0.194269,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":null,"biblio":{"volume":"63","issue":null,"first_page":"1","last_page":"4"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T11417","display_name":"Advancements in PLL and VCO Technologies","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T11417","display_name":"Advancements in PLL and VCO Technologies","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11032","display_name":"VLSI and Analog Circuit Testing","score":0.9998000264167786,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10323","display_name":"Analog and Mixed-Signal Circuit Design","score":0.9994000196456909,"subfield":{"id":"https://openalex.org/subfields/2204","display_name":"Biomedical Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/serdes","display_name":"SerDes","score":0.8493145108222961},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.7632516622543335},{"id":"https://openalex.org/keywords/verilog","display_name":"Verilog","score":0.7383871078491211},{"id":"https://openalex.org/keywords/jitter","display_name":"Jitter","score":0.6875671148300171},{"id":"https://openalex.org/keywords/field-programmable-gate-array","display_name":"Field-programmable gate array","score":0.6484561562538147},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.5376628041267395},{"id":"https://openalex.org/keywords/computer-hardware","display_name":"Computer hardware","score":0.5286498665809631},{"id":"https://openalex.org/keywords/compiler","display_name":"Compiler","score":0.4299708604812622},{"id":"https://openalex.org/keywords/key","display_name":"Key (lock)","score":0.4115979075431824},{"id":"https://openalex.org/keywords/operating-system","display_name":"Operating system","score":0.10208562016487122}],"concepts":[{"id":"https://openalex.org/C19707634","wikidata":"https://www.wikidata.org/wiki/Q6510662","display_name":"SerDes","level":2,"score":0.8493145108222961},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.7632516622543335},{"id":"https://openalex.org/C2779030575","wikidata":"https://www.wikidata.org/wiki/Q827773","display_name":"Verilog","level":3,"score":0.7383871078491211},{"id":"https://openalex.org/C134652429","wikidata":"https://www.wikidata.org/wiki/Q1052698","display_name":"Jitter","level":2,"score":0.6875671148300171},{"id":"https://openalex.org/C42935608","wikidata":"https://www.wikidata.org/wiki/Q190411","display_name":"Field-programmable gate array","level":2,"score":0.6484561562538147},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.5376628041267395},{"id":"https://openalex.org/C9390403","wikidata":"https://www.wikidata.org/wiki/Q3966","display_name":"Computer hardware","level":1,"score":0.5286498665809631},{"id":"https://openalex.org/C169590947","wikidata":"https://www.wikidata.org/wiki/Q47506","display_name":"Compiler","level":2,"score":0.4299708604812622},{"id":"https://openalex.org/C26517878","wikidata":"https://www.wikidata.org/wiki/Q228039","display_name":"Key (lock)","level":2,"score":0.4115979075431824},{"id":"https://openalex.org/C111919701","wikidata":"https://www.wikidata.org/wiki/Q9135","display_name":"Operating system","level":1,"score":0.10208562016487122},{"id":"https://openalex.org/C76155785","wikidata":"https://www.wikidata.org/wiki/Q418","display_name":"Telecommunications","level":1,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/icm.2017.8268824","is_oa":false,"landing_page_url":"https://doi.org/10.1109/icm.2017.8268824","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2017 29th International Conference on Microelectronics (ICM)","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[{"display_name":"Affordable and clean energy","score":0.8799999952316284,"id":"https://metadata.un.org/sdg/7"}],"awards":[],"funders":[{"id":"https://openalex.org/F4320330328","display_name":"Ajman University","ror":"https://ror.org/01j1rma10"}],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":13,"referenced_works":["https://openalex.org/W2023578223","https://openalex.org/W2048328919","https://openalex.org/W2108014838","https://openalex.org/W2118565267","https://openalex.org/W2123931172","https://openalex.org/W2131484509","https://openalex.org/W2139145168","https://openalex.org/W2141825982","https://openalex.org/W2176101535","https://openalex.org/W2221085202","https://openalex.org/W2412004170","https://openalex.org/W2550327407","https://openalex.org/W2561052302"],"related_works":["https://openalex.org/W1933111953","https://openalex.org/W2003312501","https://openalex.org/W2091946342","https://openalex.org/W1520599922","https://openalex.org/W2510718891","https://openalex.org/W2126574816","https://openalex.org/W2624154251","https://openalex.org/W2102417914","https://openalex.org/W653725568","https://openalex.org/W192291305"],"abstract_inverted_index":{"This":[0],"paper":[1],"presents":[2],"an":[3,71,80],"only":[4],"hardware":[5],"description":[6],"language":[7],"(HDL)-based":[8],"serial":[9],"link":[10,122],"(SerDes)":[11],"design":[12,73],"that":[13],"has":[14,44],"been":[15,45],"synthesized":[16],"on":[17],"Altera":[18],"DE2-70":[19],"FPGA":[20],"board":[21],"as":[22,79,88],"a":[23,97,104,109,124,131],"quick":[24],"proof":[25],"of":[26,127,149],"concept":[27],"for":[28,84,101],"validation":[29],"purpose.":[30],"Though":[31],"some":[32],"blocks":[33,95],"are":[34],"adopted":[35],"from":[36],"their":[37],"analog":[38,54],"counterpart":[39],"however":[40],"the":[41,48,120,147],"entire":[42],"architecture":[43],"implemented":[46],"using":[47],"Verilog":[49],"language,":[50],"hence":[51],"requires":[52],"no":[53],"or":[55],"off-chip":[56],"components":[57],"and":[58,63,82,90,108,112,130,143],"exhibit":[59],"better":[60],"power":[61,125],"efficiency":[62,126],"jitter":[64],"but":[65],"lower":[66,136],"data":[67,113],"rate.":[68],"Furthermore,":[69],"being":[70],"HDL-based":[72],"makes":[74],"it":[75],"easy":[76],"to":[77,152],"implement":[78],"IC":[81],"suitable":[83],"certain":[85],"applications":[86],"such":[87],"multicore":[89],"NoC":[91],"architectures.":[92],"Key":[93],"circuit":[94],"include":[96],"built-in":[98],"PRBS":[99],"generator":[100],"testing":[102],"purpose,":[103],"clock":[105,111],"generation":[106],"circuit,":[107],"quarter-rate":[110],"recovery":[114],"(CDR)":[115],"circuit.":[116],"Including":[117],"FPGA's":[118],"peripherals,":[119],"proposed":[121],"achieves":[123],"5.79":[128],"pW/b/s":[129],"bit":[132],"error":[133],"rate":[134],"(BER)":[135],"than":[137],"10":[138],"<sup":[139],"xmlns:mml=\"http://www.w3.org/1998/Math/MathML\"":[140],"xmlns:xlink=\"http://www.w3.org/1999/xlink\">-12</sup>":[141],",":[142],"operates":[144],"continuously":[145],"over":[146],"range":[148],"167.32":[150],"Mb/s":[151],"193.6":[153],"Mb/s.":[154]},"counts_by_year":[],"updated_date":"2025-11-06T03:46:38.306776","created_date":"2025-10-10T00:00:00"}