{"id":"https://openalex.org/W1573658396","doi":"https://doi.org/10.1109/icit.2015.7125323","title":"Performance improvements in a modern hardware design environment for control applications","display_name":"Performance improvements in a modern hardware design environment for control applications","publication_year":2015,"publication_date":"2015-03-01","ids":{"openalex":"https://openalex.org/W1573658396","doi":"https://doi.org/10.1109/icit.2015.7125323","mag":"1573658396"},"language":"en","primary_location":{"id":"doi:10.1109/icit.2015.7125323","is_oa":false,"landing_page_url":"https://doi.org/10.1109/icit.2015.7125323","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2015 IEEE International Conference on Industrial Technology (ICIT)","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5083391397","display_name":"Christoforos Economakos","orcid":null},"institutions":[{"id":"https://openalex.org/I51955386","display_name":"Technological Educational Institute of Thessaly","ror":"https://ror.org/04056ja87","country_code":"GR","type":"education","lineage":["https://openalex.org/I51955386"]}],"countries":["GR"],"is_corresponding":true,"raw_author_name":"Christoforos Economakos","raw_affiliation_strings":["Department of Automation Engineering, Technological Educational Institution of Sterea Ellada, Psahna, Greece","Technological Educational Institution of Sterea Ellada, Department of Automation Engineering, GR34400 Psahna, Evia, Greece"],"affiliations":[{"raw_affiliation_string":"Department of Automation Engineering, Technological Educational Institution of Sterea Ellada, Psahna, Greece","institution_ids":["https://openalex.org/I51955386"]},{"raw_affiliation_string":"Technological Educational Institution of Sterea Ellada, Department of Automation Engineering, GR34400 Psahna, Evia, Greece","institution_ids":["https://openalex.org/I51955386"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5037113478","display_name":"Maria P. Tzamtzi","orcid":"https://orcid.org/0009-0008-8930-1024"},"institutions":[{"id":"https://openalex.org/I51955386","display_name":"Technological Educational Institute of Thessaly","ror":"https://ror.org/04056ja87","country_code":"GR","type":"education","lineage":["https://openalex.org/I51955386"]}],"countries":["GR"],"is_corresponding":false,"raw_author_name":"Maria Tzamtzi","raw_affiliation_strings":["Department of Automation Engineering, Technological Educational Institution of Sterea Ellada, Psahna, Greece","Technological Educational Institution of Sterea Ellada, Department of Automation Engineering, GR34400 Psahna, Evia, Greece"],"affiliations":[{"raw_affiliation_string":"Department of Automation Engineering, Technological Educational Institution of Sterea Ellada, Psahna, Greece","institution_ids":["https://openalex.org/I51955386"]},{"raw_affiliation_string":"Technological Educational Institution of Sterea Ellada, Department of Automation Engineering, GR34400 Psahna, Evia, Greece","institution_ids":["https://openalex.org/I51955386"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5016630838","display_name":"M. G. Skarpetis","orcid":"https://orcid.org/0000-0002-4252-6305"},"institutions":[{"id":"https://openalex.org/I51955386","display_name":"Technological Educational Institute of Thessaly","ror":"https://ror.org/04056ja87","country_code":"GR","type":"education","lineage":["https://openalex.org/I51955386"]}],"countries":["GR"],"is_corresponding":false,"raw_author_name":"Michael Skarpetis","raw_affiliation_strings":["Department of Automation Engineering, Technological Educational Institution of Sterea Ellada, Psahna, Greece","Technological Educational Institution of Sterea Ellada, Department of Automation Engineering, GR34400 Psahna, Evia, Greece"],"affiliations":[{"raw_affiliation_string":"Department of Automation Engineering, Technological Educational Institution of Sterea Ellada, Psahna, Greece","institution_ids":["https://openalex.org/I51955386"]},{"raw_affiliation_string":"Technological Educational Institution of Sterea Ellada, Department of Automation Engineering, GR34400 Psahna, Evia, Greece","institution_ids":["https://openalex.org/I51955386"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5089110665","display_name":"George Economakos","orcid":null},"institutions":[{"id":"https://openalex.org/I174458059","display_name":"National Technical University of Athens","ror":"https://ror.org/03cx6bg69","country_code":"GR","type":"education","lineage":["https://openalex.org/I174458059"]},{"id":"https://openalex.org/I51955386","display_name":"Technological Educational Institute of Thessaly","ror":"https://ror.org/04056ja87","country_code":"GR","type":"education","lineage":["https://openalex.org/I51955386"]}],"countries":["GR"],"is_corresponding":false,"raw_author_name":"George Economakos","raw_affiliation_strings":["Department of Automation Engineering, Technological Educational Institution of Sterea Ellada, Psahna, Greece","National Technical University of Athens, School of Electrical and Computer Engineering, Microprocessors and Digital Systems Laboratory, Heroon Polytechniou 9, GR-15780 Zografou, Athens, Greece"],"affiliations":[{"raw_affiliation_string":"Department of Automation Engineering, Technological Educational Institution of Sterea Ellada, Psahna, Greece","institution_ids":["https://openalex.org/I51955386"]},{"raw_affiliation_string":"National Technical University of Athens, School of Electrical and Computer Engineering, Microprocessors and Digital Systems Laboratory, Heroon Polytechniou 9, GR-15780 Zografou, Athens, Greece","institution_ids":["https://openalex.org/I174458059"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":4,"corresponding_author_ids":["https://openalex.org/A5083391397"],"corresponding_institution_ids":["https://openalex.org/I51955386"],"apc_list":null,"apc_paid":null,"fwci":0.9689,"has_fulltext":false,"cited_by_count":3,"citation_normalized_percentile":{"value":0.74200234,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":90,"max":94},"biblio":{"volume":null,"issue":null,"first_page":"1587","last_page":"1592"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10904","display_name":"Embedded Systems Design Techniques","score":0.9997000098228455,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10904","display_name":"Embedded Systems Design Techniques","score":0.9997000098228455,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10054","display_name":"Parallel Computing and Optimization Techniques","score":0.9994000196456909,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10323","display_name":"Analog and Mixed-Signal Circuit Design","score":0.9968000054359436,"subfield":{"id":"https://openalex.org/subfields/2204","display_name":"Biomedical Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.6692953705787659},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.6059955358505249},{"id":"https://openalex.org/keywords/field-programmable-gate-array","display_name":"Field-programmable gate array","score":0.5749036073684692},{"id":"https://openalex.org/keywords/digital-signal-processing","display_name":"Digital signal processing","score":0.5230777859687805},{"id":"https://openalex.org/keywords/flexibility","display_name":"Flexibility (engineering)","score":0.5166109204292297},{"id":"https://openalex.org/keywords/multi-core-processor","display_name":"Multi-core processor","score":0.5070004463195801},{"id":"https://openalex.org/keywords/microcontroller","display_name":"Microcontroller","score":0.5008640289306641},{"id":"https://openalex.org/keywords/computer-architecture","display_name":"Computer architecture","score":0.4749439060688019},{"id":"https://openalex.org/keywords/high-level-synthesis","display_name":"High-level synthesis","score":0.4723694920539856},{"id":"https://openalex.org/keywords/electronic-system-level-design-and-verification","display_name":"Electronic system-level design and verification","score":0.4584142863750458},{"id":"https://openalex.org/keywords/computer-hardware","display_name":"Computer hardware","score":0.36766111850738525}],"concepts":[{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.6692953705787659},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.6059955358505249},{"id":"https://openalex.org/C42935608","wikidata":"https://www.wikidata.org/wiki/Q190411","display_name":"Field-programmable gate array","level":2,"score":0.5749036073684692},{"id":"https://openalex.org/C84462506","wikidata":"https://www.wikidata.org/wiki/Q173142","display_name":"Digital signal processing","level":2,"score":0.5230777859687805},{"id":"https://openalex.org/C2780598303","wikidata":"https://www.wikidata.org/wiki/Q65921492","display_name":"Flexibility (engineering)","level":2,"score":0.5166109204292297},{"id":"https://openalex.org/C78766204","wikidata":"https://www.wikidata.org/wiki/Q555032","display_name":"Multi-core processor","level":2,"score":0.5070004463195801},{"id":"https://openalex.org/C173018170","wikidata":"https://www.wikidata.org/wiki/Q165678","display_name":"Microcontroller","level":2,"score":0.5008640289306641},{"id":"https://openalex.org/C118524514","wikidata":"https://www.wikidata.org/wiki/Q173212","display_name":"Computer architecture","level":1,"score":0.4749439060688019},{"id":"https://openalex.org/C58013763","wikidata":"https://www.wikidata.org/wiki/Q5754574","display_name":"High-level synthesis","level":3,"score":0.4723694920539856},{"id":"https://openalex.org/C77495112","wikidata":"https://www.wikidata.org/wiki/Q5358436","display_name":"Electronic system-level design and verification","level":2,"score":0.4584142863750458},{"id":"https://openalex.org/C9390403","wikidata":"https://www.wikidata.org/wiki/Q3966","display_name":"Computer hardware","level":1,"score":0.36766111850738525},{"id":"https://openalex.org/C111919701","wikidata":"https://www.wikidata.org/wiki/Q9135","display_name":"Operating system","level":1,"score":0.0},{"id":"https://openalex.org/C33923547","wikidata":"https://www.wikidata.org/wiki/Q395","display_name":"Mathematics","level":0,"score":0.0},{"id":"https://openalex.org/C105795698","wikidata":"https://www.wikidata.org/wiki/Q12483","display_name":"Statistics","level":1,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/icit.2015.7125323","is_oa":false,"landing_page_url":"https://doi.org/10.1109/icit.2015.7125323","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2015 IEEE International Conference on Industrial Technology (ICIT)","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[],"awards":[],"funders":[{"id":"https://openalex.org/F4320321038","display_name":"Fonds National de la Recherche Luxembourg","ror":"https://ror.org/039z13y21"}],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":16,"referenced_works":["https://openalex.org/W1604677972","https://openalex.org/W1691307101","https://openalex.org/W2006932449","https://openalex.org/W2007222857","https://openalex.org/W2021882684","https://openalex.org/W2056302270","https://openalex.org/W2060943953","https://openalex.org/W2064057042","https://openalex.org/W2094998159","https://openalex.org/W2100183523","https://openalex.org/W2129788823","https://openalex.org/W2138719480","https://openalex.org/W2157505081","https://openalex.org/W2182349853","https://openalex.org/W2482246557","https://openalex.org/W6685848413"],"related_works":["https://openalex.org/W1980880153","https://openalex.org/W1978911128","https://openalex.org/W2156420848","https://openalex.org/W2085879890","https://openalex.org/W2042762783","https://openalex.org/W2511661872","https://openalex.org/W413444773","https://openalex.org/W2269990635","https://openalex.org/W2058369727","https://openalex.org/W2085480040"],"abstract_inverted_index":{"Digital":[0,38],"design":[1,73,86,92,99,115,120,181],"is":[2],"growing":[3],"rapidly":[4],"during":[5],"the":[6,119,135],"last":[7],"years,":[8],"offering":[9],"advanced":[10],"implementation":[11,68],"solutions":[12],"for":[13,128],"a":[14,27,61,107,111,126,168,191],"diversity":[15],"of":[16,64,121,134,145,152,162],"appliances":[17],"and":[18,23,100,110,160,171,190],"instruments,":[19],"integrating":[20],"different":[21],"sensors":[22],"actuators.":[24],"This":[25,104],"has":[26],"great":[28],"impact":[29],"on":[30],"embedded":[31],"computing,":[32],"where":[33],"high":[34,192],"performance":[35,141,188],"Embedded":[36],"Controllers,":[37],"Signal":[39],"Processor":[40],"(DSP)":[41],"chips":[42],"and,":[43],"more":[44],"recently,":[45],"power":[46],"efficient":[47,72],"Field":[48],"Programmable":[49],"Gate":[50],"Arrays":[51],"(FPGAs),":[52],"connected":[53],"into":[54],"heterogeneous":[55],"multicore":[56,108],"architectures,":[57],"are":[58,88],"found":[59],"in":[60,118],"diverse":[62],"range":[63],"applications.":[65,131],"Such":[66],"new":[67,85,91],"platforms":[69],"bring":[70],"together":[71],"methodologies,":[74],"like":[75,94],"high-level":[76],"or":[77],"C":[78,179],"level":[79,180],"hardware":[80,143],"design.":[81],"In":[82],"their":[83],"turn,":[84],"methodologies":[87],"accompanied":[89],"by":[90,167,176],"technologies":[93],"Electronic":[95],"System":[96],"Level":[97],"(ESL)":[98],"High-Level":[101],"Synthesis":[102],"(HLS).":[103],"paper":[105],"presents":[106],"architecture":[109],"corresponding":[112],"HLS":[113],"based":[114],"methodology":[116,137],"applied":[117],"demanding":[122,146],"digital":[123],"controllers,":[124],"as":[125],"reference":[127],"modern":[129],"control":[130],"The":[132],"advantages":[133],"proposed":[136],"are:":[138],"(a)":[139],"improved":[140,150,173],"through":[142],"acceleration":[144],"application":[147],"cores,":[148],"(b)":[149],"quality":[151],"results":[153,185],"with":[154,178,195],"floating":[155],"point":[156],"calculations,":[157],"(c)":[158],"flexibility":[159],"integration":[161],"common":[163],"peripheral":[164],"devices":[165],"supported":[166],"RISC":[169],"microcontroller":[170],"(d)":[172],"designer":[174],"productivity":[175,193],"working":[177],"descriptions":[182],"only.":[183],"Experimental":[184],"show":[186],"substantial":[187],"improvements":[189],"boost,":[194],"very":[196],"promising":[197],"future":[198],"extension":[199],"capabilities.":[200]},"counts_by_year":[{"year":2018,"cited_by_count":1},{"year":2016,"cited_by_count":1},{"year":2015,"cited_by_count":1}],"updated_date":"2025-11-06T03:46:38.306776","created_date":"2025-10-10T00:00:00"}