{"id":"https://openalex.org/W1966292268","doi":"https://doi.org/10.1109/icics.2011.6173516","title":"ePUMA embedded parallel DSP processor with Unique Memory Access","display_name":"ePUMA embedded parallel DSP processor with Unique Memory Access","publication_year":2011,"publication_date":"2011-12-01","ids":{"openalex":"https://openalex.org/W1966292268","doi":"https://doi.org/10.1109/icics.2011.6173516","mag":"1966292268"},"language":"en","primary_location":{"id":"doi:10.1109/icics.2011.6173516","is_oa":false,"landing_page_url":"https://doi.org/10.1109/icics.2011.6173516","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2011 8th International Conference on Information, Communications & Signal Processing","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5011014977","display_name":"Dake Liu","orcid":"https://orcid.org/0000-0002-4644-4892"},"institutions":[{"id":"https://openalex.org/I102134673","display_name":"Link\u00f6ping University","ror":"https://ror.org/05ynxx418","country_code":"SE","type":"education","lineage":["https://openalex.org/I102134673"]},{"id":"https://openalex.org/I125839683","display_name":"Beijing Institute of Technology","ror":"https://ror.org/01skt4w74","country_code":"CN","type":"education","lineage":["https://openalex.org/I125839683","https://openalex.org/I890469752"]}],"countries":["CN","SE"],"is_corresponding":true,"raw_author_name":"Dake Liu","raw_affiliation_strings":["ASIP, College of Information and electronics, Beijing Institute of Technology, China","Department of Electrical Engineering, Link\u00f6ping University, Sweden"],"affiliations":[{"raw_affiliation_string":"ASIP, College of Information and electronics, Beijing Institute of Technology, China","institution_ids":["https://openalex.org/I125839683"]},{"raw_affiliation_string":"Department of Electrical Engineering, Link\u00f6ping University, Sweden","institution_ids":["https://openalex.org/I102134673"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5111853008","display_name":"Andr\u00e9as Karlsson","orcid":null},"institutions":[{"id":"https://openalex.org/I102134673","display_name":"Link\u00f6ping University","ror":"https://ror.org/05ynxx418","country_code":"SE","type":"education","lineage":["https://openalex.org/I102134673"]}],"countries":["SE"],"is_corresponding":false,"raw_author_name":"A. Karlsson","raw_affiliation_strings":["Department of Electrical Engineering, Link\u00f6ping University, Sweden"],"affiliations":[{"raw_affiliation_string":"Department of Electrical Engineering, Link\u00f6ping University, Sweden","institution_ids":["https://openalex.org/I102134673"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5005039848","display_name":"John Sohl","orcid":null},"institutions":[{"id":"https://openalex.org/I102134673","display_name":"Link\u00f6ping University","ror":"https://ror.org/05ynxx418","country_code":"SE","type":"education","lineage":["https://openalex.org/I102134673"]}],"countries":["SE"],"is_corresponding":false,"raw_author_name":"J. Sohl","raw_affiliation_strings":["Department of Electrical Engineering, Link\u00f6ping University, Sweden"],"affiliations":[{"raw_affiliation_string":"Department of Electrical Engineering, Link\u00f6ping University, Sweden","institution_ids":["https://openalex.org/I102134673"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5100370333","display_name":"Jian Wang","orcid":"https://orcid.org/0000-0001-5416-0649"},"institutions":[{"id":"https://openalex.org/I102134673","display_name":"Link\u00f6ping University","ror":"https://ror.org/05ynxx418","country_code":"SE","type":"education","lineage":["https://openalex.org/I102134673"]}],"countries":["SE"],"is_corresponding":false,"raw_author_name":"Jian Wang","raw_affiliation_strings":["Department of Electrical Engineering, Link\u00f6ping University, Sweden"],"affiliations":[{"raw_affiliation_string":"Department of Electrical Engineering, Link\u00f6ping University, Sweden","institution_ids":["https://openalex.org/I102134673"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5039092172","display_name":"M. Petersson","orcid":null},"institutions":[{"id":"https://openalex.org/I102134673","display_name":"Link\u00f6ping University","ror":"https://ror.org/05ynxx418","country_code":"SE","type":"education","lineage":["https://openalex.org/I102134673"]}],"countries":["SE"],"is_corresponding":false,"raw_author_name":"M. Petersson","raw_affiliation_strings":["Department of Electrical Engineering, Link\u00f6ping University, Sweden"],"affiliations":[{"raw_affiliation_string":"Department of Electrical Engineering, Link\u00f6ping University, Sweden","institution_ids":["https://openalex.org/I102134673"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5100909012","display_name":"Wenbiao Zhou","orcid":null},"institutions":[{"id":"https://openalex.org/I125839683","display_name":"Beijing Institute of Technology","ror":"https://ror.org/01skt4w74","country_code":"CN","type":"education","lineage":["https://openalex.org/I125839683","https://openalex.org/I890469752"]}],"countries":["CN"],"is_corresponding":false,"raw_author_name":"Wenbiao Zhou","raw_affiliation_strings":["ASIP, College of Information and electronics, Beijing Institute of Technology, China"],"affiliations":[{"raw_affiliation_string":"ASIP, College of Information and electronics, Beijing Institute of Technology, China","institution_ids":["https://openalex.org/I125839683"]}]}],"institutions":[],"countries_distinct_count":2,"institutions_distinct_count":6,"corresponding_author_ids":["https://openalex.org/A5011014977"],"corresponding_institution_ids":["https://openalex.org/I102134673","https://openalex.org/I125839683"],"apc_list":null,"apc_paid":null,"fwci":1.0075,"has_fulltext":false,"cited_by_count":9,"citation_normalized_percentile":{"value":0.76472273,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":90,"max":98},"biblio":{"volume":null,"issue":null,"first_page":"1","last_page":"5"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10904","display_name":"Embedded Systems Design Techniques","score":1.0,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10904","display_name":"Embedded Systems Design Techniques","score":1.0,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10054","display_name":"Parallel Computing and Optimization Techniques","score":0.9998000264167786,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10829","display_name":"Interconnection Networks and Systems","score":0.9998000264167786,"subfield":{"id":"https://openalex.org/subfields/1705","display_name":"Computer Networks and Communications"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.8439773917198181},{"id":"https://openalex.org/keywords/simd","display_name":"SIMD","score":0.7691097259521484},{"id":"https://openalex.org/keywords/parallel-computing","display_name":"Parallel computing","score":0.5917561650276184},{"id":"https://openalex.org/keywords/digital-signal-processing","display_name":"Digital signal processing","score":0.5794287323951721},{"id":"https://openalex.org/keywords/field-programmable-gate-array","display_name":"Field-programmable gate array","score":0.4901297986507416},{"id":"https://openalex.org/keywords/computer-hardware","display_name":"Computer hardware","score":0.43959230184555054},{"id":"https://openalex.org/keywords/data-flow-diagram","display_name":"Data flow diagram","score":0.4297569990158081},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.41339412331581116},{"id":"https://openalex.org/keywords/computer-architecture","display_name":"Computer architecture","score":0.39013317227363586}],"concepts":[{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.8439773917198181},{"id":"https://openalex.org/C150552126","wikidata":"https://www.wikidata.org/wiki/Q339387","display_name":"SIMD","level":2,"score":0.7691097259521484},{"id":"https://openalex.org/C173608175","wikidata":"https://www.wikidata.org/wiki/Q232661","display_name":"Parallel computing","level":1,"score":0.5917561650276184},{"id":"https://openalex.org/C84462506","wikidata":"https://www.wikidata.org/wiki/Q173142","display_name":"Digital signal processing","level":2,"score":0.5794287323951721},{"id":"https://openalex.org/C42935608","wikidata":"https://www.wikidata.org/wiki/Q190411","display_name":"Field-programmable gate array","level":2,"score":0.4901297986507416},{"id":"https://openalex.org/C9390403","wikidata":"https://www.wikidata.org/wiki/Q3966","display_name":"Computer hardware","level":1,"score":0.43959230184555054},{"id":"https://openalex.org/C489000","wikidata":"https://www.wikidata.org/wiki/Q747385","display_name":"Data flow diagram","level":2,"score":0.4297569990158081},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.41339412331581116},{"id":"https://openalex.org/C118524514","wikidata":"https://www.wikidata.org/wiki/Q173212","display_name":"Computer architecture","level":1,"score":0.39013317227363586},{"id":"https://openalex.org/C77088390","wikidata":"https://www.wikidata.org/wiki/Q8513","display_name":"Database","level":1,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/icics.2011.6173516","is_oa":false,"landing_page_url":"https://doi.org/10.1109/icics.2011.6173516","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2011 8th International Conference on Information, Communications & Signal Processing","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[],"awards":[],"funders":[],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":8,"referenced_works":["https://openalex.org/W47391476","https://openalex.org/W1458848342","https://openalex.org/W1510808677","https://openalex.org/W1566762375","https://openalex.org/W2115294662","https://openalex.org/W2168249960","https://openalex.org/W2413525515","https://openalex.org/W6633947259"],"related_works":["https://openalex.org/W2534771569","https://openalex.org/W2037547261","https://openalex.org/W4311812695","https://openalex.org/W2117788426","https://openalex.org/W1876592433","https://openalex.org/W2083269738","https://openalex.org/W1967938402","https://openalex.org/W2386041993","https://openalex.org/W2019451907","https://openalex.org/W1608572506"],"abstract_inverted_index":{"Computing":[0],"unto":[1],"100GOPS":[2],"without":[3],"cooling":[4],"is":[5,29,48],"essential":[6,64],"for":[7,59],"high-end":[8],"embedded":[9,39],"systems":[10],"and":[11,21,61,77,92,101,112,165],"much":[12],"required":[13],"by":[14,147],"markets.":[15],"A":[16,178],"novel":[17],"master-slave":[18],"multi-SIMD":[19],"architecture":[20,155],"its":[22],"kernel":[23],"(template)":[24],"based":[25],"parallel":[26,34,75,80,84,111,160],"programming":[27],"flow":[28,164],"thus":[30],"introduced":[31],"as":[32],"a":[33],"signal":[35,57],"processing":[36,58,70],"platform,":[37],"ePUMA,":[38],"Parallel":[40],"DSP":[41],"processor":[42],"with":[43],"Unique":[44],"Memory":[45],"Access.":[46],"It":[47],"an":[49],"on":[50,173,180],"chip":[51],"multi-DSP-processor":[52],"(CMP)":[53],"targeting":[54],"to":[55,67,78,170],"predictable":[56],"communications":[60],"multimedia.":[62],"The":[63,150],"technologies":[65],"are":[66,167],"separate":[68,79],"the":[69,90,113,126,134,141,174],"of":[71,117,133,140],"control":[72],"stream":[73],"from":[74,83],"computing,":[76],"data":[81,93,118,161],"access":[82,94,119],"arithmetic":[85],"computing":[86,127],"kernels.":[87],"By":[88],"separations,":[89],"computation":[91],"can":[95,106,120,144],"be":[96,108,121,145],"orthogonal":[97],"both":[98],"in":[99,102,110],"hardware":[100,135,142,176],"programs.":[103],"Orthogonal":[104],"operations":[105],"therefore":[107,129],"executed":[109],"run":[114],"time":[115],"cost":[116],"minimized.":[122],"Benchmark":[123],"shows":[124,182],"that":[125],"performance":[128,185],"reaches":[130],"about":[131],"80%":[132],"limit.":[136],"Less":[137],"than":[138],"40%":[139],"limit":[143],"reached":[146],"normal":[148],"processors.":[149],"unique":[151,175],"SIMD":[152],"memory":[153],"subsystem":[154],"offers":[156],"programmable":[157],"conflict":[158],"free":[159],"accesses.":[162],"Programming":[163],"tools":[166],"also":[168],"developed":[169],"support":[171],"coding":[172],"architecture.":[177],"prototype":[179],"FPGA":[181],"especially":[183],"high":[184],"over":[186],"silicon":[187],"cost.":[188]},"counts_by_year":[{"year":2016,"cited_by_count":1},{"year":2015,"cited_by_count":4},{"year":2014,"cited_by_count":2},{"year":2013,"cited_by_count":2}],"updated_date":"2025-11-06T03:46:38.306776","created_date":"2025-10-10T00:00:00"}