{"id":"https://openalex.org/W4417170038","doi":"https://doi.org/10.1109/icecs66544.2025.11270474","title":"Modified Wallace-Tree Architecture Design and Implementation for High-Speed Multiplier","display_name":"Modified Wallace-Tree Architecture Design and Implementation for High-Speed Multiplier","publication_year":2025,"publication_date":"2025-11-17","ids":{"openalex":"https://openalex.org/W4417170038","doi":"https://doi.org/10.1109/icecs66544.2025.11270474"},"language":null,"primary_location":{"id":"doi:10.1109/icecs66544.2025.11270474","is_oa":false,"landing_page_url":"https://doi.org/10.1109/icecs66544.2025.11270474","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2025 32nd IEEE International Conference on Electronics, Circuits and Systems (ICECS)","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5059368105","display_name":"Bo Wu","orcid":"https://orcid.org/0000-0001-6658-6452"},"institutions":[{"id":"https://openalex.org/I75357094","display_name":"National Yunlin University of Science and Technology","ror":"https://ror.org/04qkq2m54","country_code":"TW","type":"education","lineage":["https://openalex.org/I75357094"]}],"countries":["TW"],"is_corresponding":true,"raw_author_name":"Bing-Huang Wu","raw_affiliation_strings":["National Yunlin University of Science & Technology,Department of Electronic Engineering"],"affiliations":[{"raw_affiliation_string":"National Yunlin University of Science & Technology,Department of Electronic Engineering","institution_ids":["https://openalex.org/I75357094"]}]},{"author_position":"middle","author":{"id":null,"display_name":"Tung-Chin Tsai","orcid":null},"institutions":[{"id":"https://openalex.org/I75357094","display_name":"National Yunlin University of Science and Technology","ror":"https://ror.org/04qkq2m54","country_code":"TW","type":"education","lineage":["https://openalex.org/I75357094"]}],"countries":["TW"],"is_corresponding":false,"raw_author_name":"Tung-Chin Tsai","raw_affiliation_strings":["National Yunlin University of Science & Technology,Department of Electronic Engineering"],"affiliations":[{"raw_affiliation_string":"National Yunlin University of Science & Technology,Department of Electronic Engineering","institution_ids":["https://openalex.org/I75357094"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5019598631","display_name":"Ming\u2010Hwa Sheu","orcid":"https://orcid.org/0000-0002-8417-474X"},"institutions":[{"id":"https://openalex.org/I75357094","display_name":"National Yunlin University of Science and Technology","ror":"https://ror.org/04qkq2m54","country_code":"TW","type":"education","lineage":["https://openalex.org/I75357094"]}],"countries":["TW"],"is_corresponding":false,"raw_author_name":"Ming-Hwa Sheu","raw_affiliation_strings":["National Yunlin University of Science & Technology,Department of Electronic Engineering"],"affiliations":[{"raw_affiliation_string":"National Yunlin University of Science & Technology,Department of Electronic Engineering","institution_ids":["https://openalex.org/I75357094"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5111582905","display_name":"Chung\u2010Ho Chen","orcid":null},"institutions":[{"id":"https://openalex.org/I4210158999","display_name":"National Cheng Kung University Hospital","ror":"https://ror.org/04zx3rq17","country_code":"TW","type":"healthcare","lineage":["https://openalex.org/I4210158999"]},{"id":"https://openalex.org/I91807558","display_name":"National Cheng Kung University","ror":"https://ror.org/01b8kcc49","country_code":"TW","type":"education","lineage":["https://openalex.org/I91807558"]}],"countries":["TW"],"is_corresponding":false,"raw_author_name":"Chung-Ho Chen","raw_affiliation_strings":["National Cheng-Kung University,Department of Electrical Engineering"],"affiliations":[{"raw_affiliation_string":"National Cheng-Kung University,Department of Electrical Engineering","institution_ids":["https://openalex.org/I91807558","https://openalex.org/I4210158999"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":4,"corresponding_author_ids":["https://openalex.org/A5059368105"],"corresponding_institution_ids":["https://openalex.org/I75357094"],"apc_list":null,"apc_paid":null,"fwci":0.0,"has_fulltext":false,"cited_by_count":0,"citation_normalized_percentile":{"value":0.38017983,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":null,"biblio":{"volume":null,"issue":null,"first_page":"1","last_page":"4"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":0.9664000272750854,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":0.9664000272750854,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10829","display_name":"Interconnection Networks and Systems","score":0.006300000008195639,"subfield":{"id":"https://openalex.org/subfields/1705","display_name":"Computer Networks and Communications"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10054","display_name":"Parallel Computing and Optimization Techniques","score":0.004000000189989805,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/adder","display_name":"Adder","score":0.9253000020980835},{"id":"https://openalex.org/keywords/critical-path-method","display_name":"Critical path method","score":0.6991000175476074},{"id":"https://openalex.org/keywords/booths-multiplication-algorithm","display_name":"Booth's multiplication algorithm","score":0.5641000270843506},{"id":"https://openalex.org/keywords/multiplier","display_name":"Multiplier (economics)","score":0.5230000019073486},{"id":"https://openalex.org/keywords/computation","display_name":"Computation","score":0.47040000557899475},{"id":"https://openalex.org/keywords/carry-save-adder","display_name":"Carry-save adder","score":0.46779999136924744},{"id":"https://openalex.org/keywords/path","display_name":"Path (computing)","score":0.43880000710487366},{"id":"https://openalex.org/keywords/tree","display_name":"Tree (set theory)","score":0.4171999990940094}],"concepts":[{"id":"https://openalex.org/C164620267","wikidata":"https://www.wikidata.org/wiki/Q376953","display_name":"Adder","level":3,"score":0.9253000020980835},{"id":"https://openalex.org/C115874739","wikidata":"https://www.wikidata.org/wiki/Q825377","display_name":"Critical path method","level":2,"score":0.6991000175476074},{"id":"https://openalex.org/C72475854","wikidata":"https://www.wikidata.org/wiki/Q477049","display_name":"Booth's multiplication algorithm","level":4,"score":0.5641000270843506},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.5605000257492065},{"id":"https://openalex.org/C124584101","wikidata":"https://www.wikidata.org/wiki/Q1053266","display_name":"Multiplier (economics)","level":2,"score":0.5230000019073486},{"id":"https://openalex.org/C45374587","wikidata":"https://www.wikidata.org/wiki/Q12525525","display_name":"Computation","level":2,"score":0.47040000557899475},{"id":"https://openalex.org/C3227080","wikidata":"https://www.wikidata.org/wiki/Q5046770","display_name":"Carry-save adder","level":4,"score":0.46779999136924744},{"id":"https://openalex.org/C2777735758","wikidata":"https://www.wikidata.org/wiki/Q817765","display_name":"Path (computing)","level":2,"score":0.43880000710487366},{"id":"https://openalex.org/C113174947","wikidata":"https://www.wikidata.org/wiki/Q2859736","display_name":"Tree (set theory)","level":2,"score":0.4171999990940094},{"id":"https://openalex.org/C2984118289","wikidata":"https://www.wikidata.org/wiki/Q29954","display_name":"Power consumption","level":3,"score":0.39329999685287476},{"id":"https://openalex.org/C116206932","wikidata":"https://www.wikidata.org/wiki/Q7454686","display_name":"Serial binary adder","level":4,"score":0.3926999866962433},{"id":"https://openalex.org/C94375191","wikidata":"https://www.wikidata.org/wiki/Q11205","display_name":"Arithmetic","level":1,"score":0.3815000057220459},{"id":"https://openalex.org/C163258240","wikidata":"https://www.wikidata.org/wiki/Q25342","display_name":"Power (physics)","level":2,"score":0.37700000405311584},{"id":"https://openalex.org/C9390403","wikidata":"https://www.wikidata.org/wiki/Q3966","display_name":"Computer hardware","level":1,"score":0.37549999356269836},{"id":"https://openalex.org/C14580979","wikidata":"https://www.wikidata.org/wiki/Q876049","display_name":"Very-large-scale integration","level":2,"score":0.35359999537467957},{"id":"https://openalex.org/C157922185","wikidata":"https://www.wikidata.org/wiki/Q173198","display_name":"Logic synthesis","level":3,"score":0.3433000147342682},{"id":"https://openalex.org/C131017901","wikidata":"https://www.wikidata.org/wiki/Q170451","display_name":"Logic gate","level":2,"score":0.30790001153945923},{"id":"https://openalex.org/C24326235","wikidata":"https://www.wikidata.org/wiki/Q126095","display_name":"Electronic engineering","level":1,"score":0.2924000024795532},{"id":"https://openalex.org/C90806461","wikidata":"https://www.wikidata.org/wiki/Q1144416","display_name":"Propagation delay","level":2,"score":0.2881999909877777},{"id":"https://openalex.org/C173608175","wikidata":"https://www.wikidata.org/wiki/Q232661","display_name":"Parallel computing","level":1,"score":0.27720001339912415},{"id":"https://openalex.org/C11413529","wikidata":"https://www.wikidata.org/wiki/Q8366","display_name":"Algorithm","level":1,"score":0.2694000005722046},{"id":"https://openalex.org/C190560348","wikidata":"https://www.wikidata.org/wiki/Q3245116","display_name":"Circuit design","level":2,"score":0.2671999931335449},{"id":"https://openalex.org/C198386975","wikidata":"https://www.wikidata.org/wiki/Q117785","display_name":"Finite impulse response","level":2,"score":0.2639999985694885},{"id":"https://openalex.org/C74524168","wikidata":"https://www.wikidata.org/wiki/Q1074539","display_name":"Integrated circuit design","level":2,"score":0.2612999975681305}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/icecs66544.2025.11270474","is_oa":false,"landing_page_url":"https://doi.org/10.1109/icecs66544.2025.11270474","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2025 32nd IEEE International Conference on Electronics, Circuits and Systems (ICECS)","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[],"awards":[],"funders":[],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":8,"referenced_works":["https://openalex.org/W2914247084","https://openalex.org/W4221015033","https://openalex.org/W4281678845","https://openalex.org/W4327773847","https://openalex.org/W4380303519","https://openalex.org/W4387982776","https://openalex.org/W4391759649","https://openalex.org/W4402835490"],"related_works":[],"abstract_inverted_index":{"For":[0],"the":[1,4,8,30,36,48,53,64,70,90,114],"design":[2,100],"of":[3,14,32,56],"Radix-4":[5,81],"Booth":[6],"multiplier,":[7],"critical":[9,37],"path":[10,38],"is":[11,86,93],"often":[12],"composed":[13],"carry":[15],"propagation":[16],"full":[17,33],"adders.":[18],"This":[19],"work":[20,75,84],"proposes":[21],"a":[22],"high-performance":[23],"modified":[24,49,102],"Wallace":[25,50,103],"tree":[26,51,104],"architecture,":[27],"which":[28],"reduces":[29,52],"number":[31,55],"adders":[34,42,57,61],"on":[35],"and":[39,89],"uses":[40],"half":[41,60],"to":[43,63],"reduce":[44],"computation":[45],"delay.":[46],"Besides,":[47],"total":[54],"by":[58],"two":[59],"compared":[62],"conventional":[65],"adder":[66],"array.":[67],"Implemented":[68],"using":[69],"TSMC":[71],"16nm":[72],"process,":[73],"this":[74],"realizes":[76],"an":[77],"8-bit":[78,80],"\u00d7":[79],"multiplier.":[82],"Its":[83],"frequency":[85],"100":[87],"MHz":[88],"power":[91],"consumption":[92],"61.85":[94],"uW.":[95],"From":[96],"experimental":[97],"results,":[98],"our":[99],"with":[101,113],"can":[105],"improve":[106],"at":[107],"least":[108],"44.05%":[109],"delay,":[110],"when":[111],"comparing":[112],"related":[115],"works.":[116]},"counts_by_year":[],"updated_date":"2026-04-17T18:11:37.981687","created_date":"2025-12-09T00:00:00"}