{"id":"https://openalex.org/W4311224197","doi":"https://doi.org/10.1109/icecs202256217.2022.9970999","title":"Automated Synthesis of Asynchronous Tsetlin Machines on FPGA","display_name":"Automated Synthesis of Asynchronous Tsetlin Machines on FPGA","publication_year":2022,"publication_date":"2022-10-24","ids":{"openalex":"https://openalex.org/W4311224197","doi":"https://doi.org/10.1109/icecs202256217.2022.9970999"},"language":"en","primary_location":{"id":"doi:10.1109/icecs202256217.2022.9970999","is_oa":false,"landing_page_url":"https://doi.org/10.1109/icecs202256217.2022.9970999","pdf_url":null,"source":{"id":"https://openalex.org/S4363607963","display_name":"2022 29th IEEE International Conference on Electronics, Circuits and Systems (ICECS)","issn_l":null,"issn":null,"is_oa":false,"is_in_doaj":false,"is_core":false,"host_organization":null,"host_organization_name":null,"host_organization_lineage":[],"host_organization_lineage_names":[],"type":"conference"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2022 29th IEEE International Conference on Electronics, Circuits and Systems (ICECS)","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5058902695","display_name":"Gang Mao","orcid":null},"institutions":[{"id":"https://openalex.org/I84884186","display_name":"Newcastle University","ror":"https://ror.org/01kj2bm70","country_code":"GB","type":"education","lineage":["https://openalex.org/I84884186"]},{"id":"https://openalex.org/I4210153877","display_name":"Microsystems (United Kingdom)","ror":"https://ror.org/04pvywd96","country_code":"GB","type":"company","lineage":["https://openalex.org/I4210153877"]}],"countries":["GB"],"is_corresponding":true,"raw_author_name":"Gang Mao","raw_affiliation_strings":["Microsystems Research Group, Newcastle University,Newcastle upon Tyne,UK","Microsystems Research Group, Newcastle University, Newcastle upon Tyne, UK"],"affiliations":[{"raw_affiliation_string":"Microsystems Research Group, Newcastle University,Newcastle upon Tyne,UK","institution_ids":["https://openalex.org/I84884186","https://openalex.org/I4210153877"]},{"raw_affiliation_string":"Microsystems Research Group, Newcastle University, Newcastle upon Tyne, UK","institution_ids":["https://openalex.org/I84884186","https://openalex.org/I4210153877"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5029446985","display_name":"Alex Yakovlev","orcid":"https://orcid.org/0000-0003-0826-9330"},"institutions":[{"id":"https://openalex.org/I4210153877","display_name":"Microsystems (United Kingdom)","ror":"https://ror.org/04pvywd96","country_code":"GB","type":"company","lineage":["https://openalex.org/I4210153877"]},{"id":"https://openalex.org/I84884186","display_name":"Newcastle University","ror":"https://ror.org/01kj2bm70","country_code":"GB","type":"education","lineage":["https://openalex.org/I84884186"]}],"countries":["GB"],"is_corresponding":false,"raw_author_name":"Alex Yakovlev","raw_affiliation_strings":["Microsystems Research Group, Newcastle University,Newcastle upon Tyne,UK","Microsystems Research Group, Newcastle University, Newcastle upon Tyne, UK"],"affiliations":[{"raw_affiliation_string":"Microsystems Research Group, Newcastle University,Newcastle upon Tyne,UK","institution_ids":["https://openalex.org/I84884186","https://openalex.org/I4210153877"]},{"raw_affiliation_string":"Microsystems Research Group, Newcastle University, Newcastle upon Tyne, UK","institution_ids":["https://openalex.org/I84884186","https://openalex.org/I4210153877"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5058743869","display_name":"Fei Xia","orcid":"https://orcid.org/0000-0002-3426-8406"},"institutions":[{"id":"https://openalex.org/I84884186","display_name":"Newcastle University","ror":"https://ror.org/01kj2bm70","country_code":"GB","type":"education","lineage":["https://openalex.org/I84884186"]},{"id":"https://openalex.org/I4210153877","display_name":"Microsystems (United Kingdom)","ror":"https://ror.org/04pvywd96","country_code":"GB","type":"company","lineage":["https://openalex.org/I4210153877"]}],"countries":["GB"],"is_corresponding":false,"raw_author_name":"Fei Xia","raw_affiliation_strings":["Microsystems Research Group, Newcastle University,Newcastle upon Tyne,UK","Microsystems Research Group, Newcastle University, Newcastle upon Tyne, UK"],"affiliations":[{"raw_affiliation_string":"Microsystems Research Group, Newcastle University,Newcastle upon Tyne,UK","institution_ids":["https://openalex.org/I84884186","https://openalex.org/I4210153877"]},{"raw_affiliation_string":"Microsystems Research Group, Newcastle University, Newcastle upon Tyne, UK","institution_ids":["https://openalex.org/I84884186","https://openalex.org/I4210153877"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5056355574","display_name":"Tian Lan","orcid":null},"institutions":[{"id":"https://openalex.org/I4210153877","display_name":"Microsystems (United Kingdom)","ror":"https://ror.org/04pvywd96","country_code":"GB","type":"company","lineage":["https://openalex.org/I4210153877"]},{"id":"https://openalex.org/I84884186","display_name":"Newcastle University","ror":"https://ror.org/01kj2bm70","country_code":"GB","type":"education","lineage":["https://openalex.org/I84884186"]}],"countries":["GB"],"is_corresponding":false,"raw_author_name":"Tian Lan","raw_affiliation_strings":["Microsystems Research Group, Newcastle University,Newcastle upon Tyne,UK","Microsystems Research Group, Newcastle University, Newcastle upon Tyne, UK"],"affiliations":[{"raw_affiliation_string":"Microsystems Research Group, Newcastle University,Newcastle upon Tyne,UK","institution_ids":["https://openalex.org/I84884186","https://openalex.org/I4210153877"]},{"raw_affiliation_string":"Microsystems Research Group, Newcastle University, Newcastle upon Tyne, UK","institution_ids":["https://openalex.org/I84884186","https://openalex.org/I4210153877"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5101773931","display_name":"Shengqi Yu","orcid":"https://orcid.org/0000-0001-8059-5793"},"institutions":[{"id":"https://openalex.org/I84884186","display_name":"Newcastle University","ror":"https://ror.org/01kj2bm70","country_code":"GB","type":"education","lineage":["https://openalex.org/I84884186"]},{"id":"https://openalex.org/I4210153877","display_name":"Microsystems (United Kingdom)","ror":"https://ror.org/04pvywd96","country_code":"GB","type":"company","lineage":["https://openalex.org/I4210153877"]}],"countries":["GB"],"is_corresponding":false,"raw_author_name":"Shengqi Yu","raw_affiliation_strings":["Microsystems Research Group, Newcastle University,Newcastle upon Tyne,UK","Microsystems Research Group, Newcastle University, Newcastle upon Tyne, UK"],"affiliations":[{"raw_affiliation_string":"Microsystems Research Group, Newcastle University,Newcastle upon Tyne,UK","institution_ids":["https://openalex.org/I84884186","https://openalex.org/I4210153877"]},{"raw_affiliation_string":"Microsystems Research Group, Newcastle University, Newcastle upon Tyne, UK","institution_ids":["https://openalex.org/I84884186","https://openalex.org/I4210153877"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5077777787","display_name":"Rishad Shafik","orcid":"https://orcid.org/0000-0001-5444-537X"},"institutions":[{"id":"https://openalex.org/I4210153877","display_name":"Microsystems (United Kingdom)","ror":"https://ror.org/04pvywd96","country_code":"GB","type":"company","lineage":["https://openalex.org/I4210153877"]},{"id":"https://openalex.org/I84884186","display_name":"Newcastle University","ror":"https://ror.org/01kj2bm70","country_code":"GB","type":"education","lineage":["https://openalex.org/I84884186"]}],"countries":["GB"],"is_corresponding":false,"raw_author_name":"Rishad Shafik","raw_affiliation_strings":["Microsystems Research Group, Newcastle University,Newcastle upon Tyne,UK","Microsystems Research Group, Newcastle University, Newcastle upon Tyne, UK"],"affiliations":[{"raw_affiliation_string":"Microsystems Research Group, Newcastle University,Newcastle upon Tyne,UK","institution_ids":["https://openalex.org/I84884186","https://openalex.org/I4210153877"]},{"raw_affiliation_string":"Microsystems Research Group, Newcastle University, Newcastle upon Tyne, UK","institution_ids":["https://openalex.org/I84884186","https://openalex.org/I4210153877"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":6,"corresponding_author_ids":["https://openalex.org/A5058902695"],"corresponding_institution_ids":["https://openalex.org/I4210153877","https://openalex.org/I84884186"],"apc_list":null,"apc_paid":null,"fwci":1.2863,"has_fulltext":false,"cited_by_count":6,"citation_normalized_percentile":{"value":0.7826087,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":91,"max":97},"biblio":{"volume":"40","issue":null,"first_page":"1","last_page":"4"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10054","display_name":"Parallel Computing and Optimization Techniques","score":0.9986000061035156,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10054","display_name":"Parallel Computing and Optimization Techniques","score":0.9986000061035156,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10904","display_name":"Embedded Systems Design Techniques","score":0.9947999715805054,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T12288","display_name":"Optimization and Search Problems","score":0.9919999837875366,"subfield":{"id":"https://openalex.org/subfields/1705","display_name":"Computer Networks and Communications"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/asynchronous-communication","display_name":"Asynchronous communication","score":0.8192791938781738},{"id":"https://openalex.org/keywords/field-programmable-gate-array","display_name":"Field-programmable gate array","score":0.8000404238700867},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.7906861305236816},{"id":"https://openalex.org/keywords/asynchronous-system","display_name":"Asynchronous system","score":0.5591306686401367},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.5459084510803223},{"id":"https://openalex.org/keywords/electronic-design-automation","display_name":"Electronic design automation","score":0.5304372310638428},{"id":"https://openalex.org/keywords/automation","display_name":"Automation","score":0.46925756335258484},{"id":"https://openalex.org/keywords/computer-architecture","display_name":"Computer architecture","score":0.46691420674324036},{"id":"https://openalex.org/keywords/logic-synthesis","display_name":"Logic synthesis","score":0.46548572182655334},{"id":"https://openalex.org/keywords/electronic-circuit","display_name":"Electronic circuit","score":0.42942914366722107},{"id":"https://openalex.org/keywords/computer-engineering","display_name":"Computer engineering","score":0.4044169485569},{"id":"https://openalex.org/keywords/computer-hardware","display_name":"Computer hardware","score":0.37742704153060913},{"id":"https://openalex.org/keywords/logic-gate","display_name":"Logic gate","score":0.30503565073013306},{"id":"https://openalex.org/keywords/algorithm","display_name":"Algorithm","score":0.2510250210762024},{"id":"https://openalex.org/keywords/synchronous-circuit","display_name":"Synchronous circuit","score":0.1591360867023468},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.1142737865447998},{"id":"https://openalex.org/keywords/clock-signal","display_name":"Clock signal","score":0.10849115252494812},{"id":"https://openalex.org/keywords/electrical-engineering","display_name":"Electrical engineering","score":0.0813407301902771}],"concepts":[{"id":"https://openalex.org/C151319957","wikidata":"https://www.wikidata.org/wiki/Q752739","display_name":"Asynchronous communication","level":2,"score":0.8192791938781738},{"id":"https://openalex.org/C42935608","wikidata":"https://www.wikidata.org/wiki/Q190411","display_name":"Field-programmable gate array","level":2,"score":0.8000404238700867},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.7906861305236816},{"id":"https://openalex.org/C7923308","wikidata":"https://www.wikidata.org/wiki/Q4812211","display_name":"Asynchronous system","level":5,"score":0.5591306686401367},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.5459084510803223},{"id":"https://openalex.org/C64260653","wikidata":"https://www.wikidata.org/wiki/Q1194864","display_name":"Electronic design automation","level":2,"score":0.5304372310638428},{"id":"https://openalex.org/C115901376","wikidata":"https://www.wikidata.org/wiki/Q184199","display_name":"Automation","level":2,"score":0.46925756335258484},{"id":"https://openalex.org/C118524514","wikidata":"https://www.wikidata.org/wiki/Q173212","display_name":"Computer architecture","level":1,"score":0.46691420674324036},{"id":"https://openalex.org/C157922185","wikidata":"https://www.wikidata.org/wiki/Q173198","display_name":"Logic synthesis","level":3,"score":0.46548572182655334},{"id":"https://openalex.org/C134146338","wikidata":"https://www.wikidata.org/wiki/Q1815901","display_name":"Electronic circuit","level":2,"score":0.42942914366722107},{"id":"https://openalex.org/C113775141","wikidata":"https://www.wikidata.org/wiki/Q428691","display_name":"Computer engineering","level":1,"score":0.4044169485569},{"id":"https://openalex.org/C9390403","wikidata":"https://www.wikidata.org/wiki/Q3966","display_name":"Computer hardware","level":1,"score":0.37742704153060913},{"id":"https://openalex.org/C131017901","wikidata":"https://www.wikidata.org/wiki/Q170451","display_name":"Logic gate","level":2,"score":0.30503565073013306},{"id":"https://openalex.org/C11413529","wikidata":"https://www.wikidata.org/wiki/Q8366","display_name":"Algorithm","level":1,"score":0.2510250210762024},{"id":"https://openalex.org/C42196554","wikidata":"https://www.wikidata.org/wiki/Q1186179","display_name":"Synchronous circuit","level":4,"score":0.1591360867023468},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.1142737865447998},{"id":"https://openalex.org/C137059387","wikidata":"https://www.wikidata.org/wiki/Q426882","display_name":"Clock signal","level":3,"score":0.10849115252494812},{"id":"https://openalex.org/C119599485","wikidata":"https://www.wikidata.org/wiki/Q43035","display_name":"Electrical engineering","level":1,"score":0.0813407301902771},{"id":"https://openalex.org/C78519656","wikidata":"https://www.wikidata.org/wiki/Q101333","display_name":"Mechanical engineering","level":1,"score":0.0},{"id":"https://openalex.org/C31258907","wikidata":"https://www.wikidata.org/wiki/Q1301371","display_name":"Computer network","level":1,"score":0.0},{"id":"https://openalex.org/C134652429","wikidata":"https://www.wikidata.org/wiki/Q1052698","display_name":"Jitter","level":2,"score":0.0},{"id":"https://openalex.org/C76155785","wikidata":"https://www.wikidata.org/wiki/Q418","display_name":"Telecommunications","level":1,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/icecs202256217.2022.9970999","is_oa":false,"landing_page_url":"https://doi.org/10.1109/icecs202256217.2022.9970999","pdf_url":null,"source":{"id":"https://openalex.org/S4363607963","display_name":"2022 29th IEEE International Conference on Electronics, Circuits and Systems (ICECS)","issn_l":null,"issn":null,"is_oa":false,"is_in_doaj":false,"is_core":false,"host_organization":null,"host_organization_name":null,"host_organization_lineage":[],"host_organization_lineage_names":[],"type":"conference"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2022 29th IEEE International Conference on Electronics, Circuits and Systems (ICECS)","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[{"id":"https://metadata.un.org/sdg/7","display_name":"Affordable and clean energy","score":0.8899999856948853}],"awards":[{"id":"https://openalex.org/G6143952702","display_name":null,"funder_award_id":"EP/L025507/1","funder_id":"https://openalex.org/F4320334627","funder_display_name":"Engineering and Physical Sciences Research Council"}],"funders":[{"id":"https://openalex.org/F4320334627","display_name":"Engineering and Physical Sciences Research Council","ror":"https://ror.org/0439y7842"}],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":21,"referenced_works":["https://openalex.org/W1516020365","https://openalex.org/W2009591231","https://openalex.org/W2018257140","https://openalex.org/W2029005287","https://openalex.org/W2102871594","https://openalex.org/W2166754476","https://openalex.org/W2586173475","https://openalex.org/W2795849550","https://openalex.org/W2796362437","https://openalex.org/W2908360749","https://openalex.org/W3150838188","https://openalex.org/W3198982345","https://openalex.org/W3199276130","https://openalex.org/W3216521497","https://openalex.org/W4312707169","https://openalex.org/W4312899265","https://openalex.org/W6675482867","https://openalex.org/W6684579003","https://openalex.org/W6733321200","https://openalex.org/W6750154454","https://openalex.org/W6804516782"],"related_works":["https://openalex.org/W2098419840","https://openalex.org/W1966764473","https://openalex.org/W2789349722","https://openalex.org/W1985308002","https://openalex.org/W1887481132","https://openalex.org/W2121963733","https://openalex.org/W1977171228","https://openalex.org/W2059422871","https://openalex.org/W2766377030","https://openalex.org/W4318224782"],"abstract_inverted_index":{"Implementing":[0],"custom":[1],"machine":[2],"learning":[3],"(ML)":[4],"accelerators":[5],"involves":[6,146],"running":[7],"thousands":[8],"if":[9,34],"not":[10],"millions":[11],"of":[12,15,110,113,122,135,161,171],"clock":[13],"cycles":[14],"simulations":[16],"per":[17],"training":[18],"epoch":[19],"and":[20,78,164],"is":[21,38,50,85,88],"infeasible":[22],"in":[23,55,97,132],"low-level":[24],"commercial":[25],"EDA":[26],"tools.":[27,142],"This":[28,87,104],"task":[29],"becomes":[30],"even":[31],"more":[32],"difficult":[33],"the":[35,51,93,107,120,139,155,158,179],"ML":[36,151],"hardware":[37],"asynchronous":[39,83,114],"rather":[40],"than":[41],"clocked.":[42],"Asynchronous":[43],"designs":[44],"provide":[45],"towards":[46],"significant":[47],"energy-efficiency,":[48],"which":[49],"most":[52],"important":[53,129],"challenge":[54],"artificial":[56],"intelligence":[57],"(AI)":[58],"today.":[59],"Field":[60],"programmable":[61],"gate":[62],"array":[63],"(FPGA)":[64],"based":[65],"prototyping":[66],"could":[67],"help":[68],"make":[69],"design":[70,111],"automation":[71,112],"feasible,":[72],"but":[73],"existing":[74],"FPGAs":[75,91,117],"are":[76,167],"clocked,":[77],"adapting":[79],"them":[80],"for":[81],"implementing":[82,148],"circuits":[84,115,147,172],"challenging.":[86],"primarily":[89],"because":[90],"violate":[92],"usual":[94],"timing":[95,125],"constraints":[96,126],"those":[98],"circuits,":[99],"such":[100],"as":[101,154],"isochronic":[102],"forks.":[103],"paper":[105],"addresses":[106],"core":[108],"aspect":[109],"through":[116],"by":[118],"solving":[119],"problem":[121],"mapping":[123],"critical":[124],"while":[127],"retaining":[128],"delay-insensitivity":[130],"properties":[131],"a":[133,149,162],"range":[134],"algorithms":[136],"compatible":[137],"with":[138,173],"FPGA":[140],"synthesis":[141],"Our":[143],"case":[144],"study":[145],"novel":[150],"algorithm,":[152],"known":[153],"Tsetlin":[156],"machine,":[157],"central":[159],"part":[160],"TM,":[163],"majority":[165],"voting":[166],"synthesized.":[168],"Different":[169],"scales":[170],"up":[174],"to":[175],"9513":[176],"LUTs":[177],"implement":[178],"clause":[180],"generator.":[181]},"counts_by_year":[{"year":2025,"cited_by_count":1},{"year":2024,"cited_by_count":2},{"year":2023,"cited_by_count":3}],"updated_date":"2025-11-06T03:46:38.306776","created_date":"2025-10-10T00:00:00"}