{"id":"https://openalex.org/W2786606957","doi":"https://doi.org/10.1109/icecs.2017.8292060","title":"Instruction-level programming approach for very long instruction word digital signal processors","display_name":"Instruction-level programming approach for very long instruction word digital signal processors","publication_year":2017,"publication_date":"2017-12-01","ids":{"openalex":"https://openalex.org/W2786606957","doi":"https://doi.org/10.1109/icecs.2017.8292060","mag":"2786606957"},"language":"en","primary_location":{"id":"doi:10.1109/icecs.2017.8292060","is_oa":false,"landing_page_url":"https://doi.org/10.1109/icecs.2017.8292060","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2017 24th IEEE International Conference on Electronics, Circuits and Systems (ICECS)","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5050098499","display_name":"Tom\u00e1\u0161 Fr\u00fdza","orcid":"https://orcid.org/0000-0001-7313-6142"},"institutions":[{"id":"https://openalex.org/I60587646","display_name":"Brno University of Technology","ror":"https://ror.org/03613d656","country_code":"CZ","type":"education","lineage":["https://openalex.org/I60587646"]}],"countries":["CZ"],"is_corresponding":true,"raw_author_name":"Tomas Fryza","raw_affiliation_strings":["Department of Radio Electronics, Brno University of Technology, Brno, Czech Republic"],"affiliations":[{"raw_affiliation_string":"Department of Radio Electronics, Brno University of Technology, Brno, Czech Republic","institution_ids":["https://openalex.org/I60587646"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5046606538","display_name":"Roman Mego","orcid":"https://orcid.org/0000-0003-0303-3847"},"institutions":[{"id":"https://openalex.org/I60587646","display_name":"Brno University of Technology","ror":"https://ror.org/03613d656","country_code":"CZ","type":"education","lineage":["https://openalex.org/I60587646"]}],"countries":["CZ"],"is_corresponding":false,"raw_author_name":"Roman Mego","raw_affiliation_strings":["Department of Radio Electronics, Brno University of Technology, Brno, Czech Republic"],"affiliations":[{"raw_affiliation_string":"Department of Radio Electronics, Brno University of Technology, Brno, Czech Republic","institution_ids":["https://openalex.org/I60587646"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":2,"corresponding_author_ids":["https://openalex.org/A5050098499"],"corresponding_institution_ids":["https://openalex.org/I60587646"],"apc_list":null,"apc_paid":null,"fwci":0.0,"has_fulltext":false,"cited_by_count":0,"citation_normalized_percentile":{"value":0.21919276,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":null,"biblio":{"volume":null,"issue":null,"first_page":"518","last_page":"521"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10904","display_name":"Embedded Systems Design Techniques","score":0.9995999932289124,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10904","display_name":"Embedded Systems Design Techniques","score":0.9995999932289124,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10054","display_name":"Parallel Computing and Optimization Techniques","score":0.998199999332428,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10829","display_name":"Interconnection Networks and Systems","score":0.9962000250816345,"subfield":{"id":"https://openalex.org/subfields/1705","display_name":"Computer Networks and Communications"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/very-long-instruction-word","display_name":"Very long instruction word","score":0.9281790256500244},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.8563504219055176},{"id":"https://openalex.org/keywords/digital-signal-processor","display_name":"Digital signal processor","score":0.6135667562484741},{"id":"https://openalex.org/keywords/word","display_name":"Word (group theory)","score":0.5793406963348389},{"id":"https://openalex.org/keywords/digital-signal-processing","display_name":"Digital signal processing","score":0.5595831274986267},{"id":"https://openalex.org/keywords/computer-architecture","display_name":"Computer architecture","score":0.5338246822357178},{"id":"https://openalex.org/keywords/process","display_name":"Process (computing)","score":0.529079020023346},{"id":"https://openalex.org/keywords/instruction-set","display_name":"Instruction set","score":0.5109845399856567},{"id":"https://openalex.org/keywords/parallel-computing","display_name":"Parallel computing","score":0.4667986035346985},{"id":"https://openalex.org/keywords/high-level-synthesis","display_name":"High-level synthesis","score":0.4649891257286072},{"id":"https://openalex.org/keywords/media-processor","display_name":"Media processor","score":0.44966378808021545},{"id":"https://openalex.org/keywords/high-level-programming-language","display_name":"High-level programming language","score":0.4232249855995178},{"id":"https://openalex.org/keywords/programming-language","display_name":"Programming language","score":0.3818845748901367},{"id":"https://openalex.org/keywords/arithmetic","display_name":"Arithmetic","score":0.32216352224349976},{"id":"https://openalex.org/keywords/programming-paradigm","display_name":"Programming paradigm","score":0.2702590227127075},{"id":"https://openalex.org/keywords/computer-hardware","display_name":"Computer hardware","score":0.226884663105011},{"id":"https://openalex.org/keywords/field-programmable-gate-array","display_name":"Field-programmable gate array","score":0.09647423028945923}],"concepts":[{"id":"https://openalex.org/C170595534","wikidata":"https://www.wikidata.org/wiki/Q249743","display_name":"Very long instruction word","level":2,"score":0.9281790256500244},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.8563504219055176},{"id":"https://openalex.org/C161611012","wikidata":"https://www.wikidata.org/wiki/Q106370","display_name":"Digital signal processor","level":3,"score":0.6135667562484741},{"id":"https://openalex.org/C90805587","wikidata":"https://www.wikidata.org/wiki/Q10944557","display_name":"Word (group theory)","level":2,"score":0.5793406963348389},{"id":"https://openalex.org/C84462506","wikidata":"https://www.wikidata.org/wiki/Q173142","display_name":"Digital signal processing","level":2,"score":0.5595831274986267},{"id":"https://openalex.org/C118524514","wikidata":"https://www.wikidata.org/wiki/Q173212","display_name":"Computer architecture","level":1,"score":0.5338246822357178},{"id":"https://openalex.org/C98045186","wikidata":"https://www.wikidata.org/wiki/Q205663","display_name":"Process (computing)","level":2,"score":0.529079020023346},{"id":"https://openalex.org/C202491316","wikidata":"https://www.wikidata.org/wiki/Q272683","display_name":"Instruction set","level":2,"score":0.5109845399856567},{"id":"https://openalex.org/C173608175","wikidata":"https://www.wikidata.org/wiki/Q232661","display_name":"Parallel computing","level":1,"score":0.4667986035346985},{"id":"https://openalex.org/C58013763","wikidata":"https://www.wikidata.org/wiki/Q5754574","display_name":"High-level synthesis","level":3,"score":0.4649891257286072},{"id":"https://openalex.org/C52027705","wikidata":"https://www.wikidata.org/wiki/Q6805986","display_name":"Media processor","level":4,"score":0.44966378808021545},{"id":"https://openalex.org/C19024347","wikidata":"https://www.wikidata.org/wiki/Q211496","display_name":"High-level programming language","level":3,"score":0.4232249855995178},{"id":"https://openalex.org/C199360897","wikidata":"https://www.wikidata.org/wiki/Q9143","display_name":"Programming language","level":1,"score":0.3818845748901367},{"id":"https://openalex.org/C94375191","wikidata":"https://www.wikidata.org/wiki/Q11205","display_name":"Arithmetic","level":1,"score":0.32216352224349976},{"id":"https://openalex.org/C34165917","wikidata":"https://www.wikidata.org/wiki/Q188267","display_name":"Programming paradigm","level":2,"score":0.2702590227127075},{"id":"https://openalex.org/C9390403","wikidata":"https://www.wikidata.org/wiki/Q3966","display_name":"Computer hardware","level":1,"score":0.226884663105011},{"id":"https://openalex.org/C42935608","wikidata":"https://www.wikidata.org/wiki/Q190411","display_name":"Field-programmable gate array","level":2,"score":0.09647423028945923},{"id":"https://openalex.org/C138885662","wikidata":"https://www.wikidata.org/wiki/Q5891","display_name":"Philosophy","level":0,"score":0.0},{"id":"https://openalex.org/C33923547","wikidata":"https://www.wikidata.org/wiki/Q395","display_name":"Mathematics","level":0,"score":0.0},{"id":"https://openalex.org/C41895202","wikidata":"https://www.wikidata.org/wiki/Q8162","display_name":"Linguistics","level":1,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/icecs.2017.8292060","is_oa":false,"landing_page_url":"https://doi.org/10.1109/icecs.2017.8292060","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2017 24th IEEE International Conference on Electronics, Circuits and Systems (ICECS)","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[],"awards":[],"funders":[],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":9,"referenced_works":["https://openalex.org/W1494198113","https://openalex.org/W1538924494","https://openalex.org/W1969295987","https://openalex.org/W2013878778","https://openalex.org/W2026235180","https://openalex.org/W2123229196","https://openalex.org/W2295746808","https://openalex.org/W2602798140","https://openalex.org/W6697206316"],"related_works":["https://openalex.org/W2240212289","https://openalex.org/W2104078694","https://openalex.org/W2137561381","https://openalex.org/W1851356153","https://openalex.org/W2091059919","https://openalex.org/W1588619283","https://openalex.org/W2556885209","https://openalex.org/W2100914138","https://openalex.org/W2050874000","https://openalex.org/W2123792842"],"abstract_inverted_index":{"This":[0],"paper":[1],"is":[2,30],"focused":[3],"on":[4],"the":[5,23,45,49,73],"benefit":[6],"of":[7,10,25,51,56,69],"low-level":[8],"programming":[9],"Digital":[11],"Signal":[12],"Processors":[13],"(DSPs)":[14],"with":[15],"Very":[16],"Long":[17],"Instruction":[18],"Word":[19],"(VLIW)":[20],"architecture.":[21],"Specifically,":[22],"process":[24],"hardware":[26],"resources":[27],"allocation":[28],"which":[29],"outlined":[31],"in":[32,72],"text":[33],"and":[34,62],"proved":[35],"by":[36,54],"basic":[37],"matrix":[38,60],"benchmarks.":[39],"Compared":[40],"to":[41,65],"available":[42],"library":[43],"functions,":[44],"proposed":[46],"results":[47],"decrease":[48],"number":[50],"execution":[52],"cycles":[53],"tens":[55],"percent":[57],"for":[58],"smaller":[59],"dimensions":[61],"help":[63],"developers":[64],"solve":[66],"critical":[67],"parts":[68],"their":[70],"applications":[71],"instruction-level":[74],"approach.":[75]},"counts_by_year":[],"updated_date":"2025-11-06T03:46:38.306776","created_date":"2025-10-10T00:00:00"}