{"id":"https://openalex.org/W2307265660","doi":"https://doi.org/10.1109/icecs.2015.7440313","title":"A platform-based design framework to boost many-core software development","display_name":"A platform-based design framework to boost many-core software development","publication_year":2015,"publication_date":"2015-12-01","ids":{"openalex":"https://openalex.org/W2307265660","doi":"https://doi.org/10.1109/icecs.2015.7440313","mag":"2307265660"},"language":"en","primary_location":{"id":"doi:10.1109/icecs.2015.7440313","is_oa":false,"landing_page_url":"https://doi.org/10.1109/icecs.2015.7440313","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2015 IEEE International Conference on Electronics, Circuits, and Systems (ICECS)","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":true,"oa_status":"green","oa_url":"https://figshare.com/articles/conference_contribution/A_platform-based_design_framework_to_boost_many-core_software_development/10144127","any_repository_has_fulltext":true},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5051066547","display_name":"Guilherme Madalozzo","orcid":"https://orcid.org/0000-0002-1519-4165"},"institutions":[{"id":"https://openalex.org/I45643870","display_name":"Pontif\u00edcia Universidade Cat\u00f3lica do Rio Grande do Sul","ror":"https://ror.org/025vmq686","country_code":"BR","type":"education","lineage":["https://openalex.org/I45643870"]}],"countries":["BR"],"is_corresponding":true,"raw_author_name":"Guilherme Madalozzo","raw_affiliation_strings":["FACIN - PUCRS - Av, Porto Alegre, Brazil"],"affiliations":[{"raw_affiliation_string":"FACIN - PUCRS - Av, Porto Alegre, Brazil","institution_ids":["https://openalex.org/I45643870"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5025001597","display_name":"Marcelo Mandelli","orcid":null},"institutions":[{"id":"https://openalex.org/I45643870","display_name":"Pontif\u00edcia Universidade Cat\u00f3lica do Rio Grande do Sul","ror":"https://ror.org/025vmq686","country_code":"BR","type":"education","lineage":["https://openalex.org/I45643870"]}],"countries":["BR"],"is_corresponding":false,"raw_author_name":"Marcelo Mandelli","raw_affiliation_strings":["FACIN - PUCRS - Av, Porto Alegre, Brazil"],"affiliations":[{"raw_affiliation_string":"FACIN - PUCRS - Av, Porto Alegre, Brazil","institution_ids":["https://openalex.org/I45643870"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5080883695","display_name":"Luciano Ost","orcid":"https://orcid.org/0000-0002-5160-5232"},"institutions":[{"id":"https://openalex.org/I153648349","display_name":"University of Leicester","ror":"https://ror.org/04h699437","country_code":"GB","type":"education","lineage":["https://openalex.org/I153648349"]}],"countries":["GB"],"is_corresponding":false,"raw_author_name":"Luciano Ost","raw_affiliation_strings":["Department of Engineering, University of Leicester, Leicester, UK"],"affiliations":[{"raw_affiliation_string":"Department of Engineering, University of Leicester, Leicester, UK","institution_ids":["https://openalex.org/I153648349"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5025418231","display_name":"Fernando Moraes","orcid":"https://orcid.org/0000-0001-6126-6847"},"institutions":[{"id":"https://openalex.org/I45643870","display_name":"Pontif\u00edcia Universidade Cat\u00f3lica do Rio Grande do Sul","ror":"https://ror.org/025vmq686","country_code":"BR","type":"education","lineage":["https://openalex.org/I45643870"]}],"countries":["BR"],"is_corresponding":false,"raw_author_name":"Fernando G. Moraes","raw_affiliation_strings":["FACIN - PUCRS - Av, Porto Alegre, Brazil"],"affiliations":[{"raw_affiliation_string":"FACIN - PUCRS - Av, Porto Alegre, Brazil","institution_ids":["https://openalex.org/I45643870"]}]}],"institutions":[],"countries_distinct_count":2,"institutions_distinct_count":4,"corresponding_author_ids":["https://openalex.org/A5051066547"],"corresponding_institution_ids":["https://openalex.org/I45643870"],"apc_list":null,"apc_paid":null,"fwci":0.0,"has_fulltext":false,"cited_by_count":2,"citation_normalized_percentile":{"value":0.1640038,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":89,"max":94},"biblio":{"volume":null,"issue":null,"first_page":"320","last_page":"323"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10904","display_name":"Embedded Systems Design Techniques","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10904","display_name":"Embedded Systems Design Techniques","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10829","display_name":"Interconnection Networks and Systems","score":0.9998000264167786,"subfield":{"id":"https://openalex.org/subfields/1705","display_name":"Computer Networks and Communications"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10933","display_name":"Real-Time Systems Scheduling","score":0.9995999932289124,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/systemc","display_name":"SystemC","score":0.9663059711456299},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.8064637184143066},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.6826766133308411},{"id":"https://openalex.org/keywords/vhdl","display_name":"VHDL","score":0.6609222888946533},{"id":"https://openalex.org/keywords/computer-architecture","display_name":"Computer architecture","score":0.5736004710197449},{"id":"https://openalex.org/keywords/software","display_name":"Software","score":0.4874536991119385},{"id":"https://openalex.org/keywords/electronic-system-level-design-and-verification","display_name":"Electronic system-level design and verification","score":0.4669056534767151},{"id":"https://openalex.org/keywords/high-level-synthesis","display_name":"High-level synthesis","score":0.45350009202957153},{"id":"https://openalex.org/keywords/embedded-software","display_name":"Embedded software","score":0.44959795475006104},{"id":"https://openalex.org/keywords/design-flow","display_name":"Design flow","score":0.44251322746276855},{"id":"https://openalex.org/keywords/operating-system","display_name":"Operating system","score":0.30138856172561646},{"id":"https://openalex.org/keywords/field-programmable-gate-array","display_name":"Field-programmable gate array","score":0.20452848076820374}],"concepts":[{"id":"https://openalex.org/C2776928060","wikidata":"https://www.wikidata.org/wiki/Q1753563","display_name":"SystemC","level":2,"score":0.9663059711456299},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.8064637184143066},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.6826766133308411},{"id":"https://openalex.org/C36941000","wikidata":"https://www.wikidata.org/wiki/Q209455","display_name":"VHDL","level":3,"score":0.6609222888946533},{"id":"https://openalex.org/C118524514","wikidata":"https://www.wikidata.org/wiki/Q173212","display_name":"Computer architecture","level":1,"score":0.5736004710197449},{"id":"https://openalex.org/C2777904410","wikidata":"https://www.wikidata.org/wiki/Q7397","display_name":"Software","level":2,"score":0.4874536991119385},{"id":"https://openalex.org/C77495112","wikidata":"https://www.wikidata.org/wiki/Q5358436","display_name":"Electronic system-level design and verification","level":2,"score":0.4669056534767151},{"id":"https://openalex.org/C58013763","wikidata":"https://www.wikidata.org/wiki/Q5754574","display_name":"High-level synthesis","level":3,"score":0.45350009202957153},{"id":"https://openalex.org/C154488198","wikidata":"https://www.wikidata.org/wiki/Q1335007","display_name":"Embedded software","level":3,"score":0.44959795475006104},{"id":"https://openalex.org/C37135326","wikidata":"https://www.wikidata.org/wiki/Q931942","display_name":"Design flow","level":2,"score":0.44251322746276855},{"id":"https://openalex.org/C111919701","wikidata":"https://www.wikidata.org/wiki/Q9135","display_name":"Operating system","level":1,"score":0.30138856172561646},{"id":"https://openalex.org/C42935608","wikidata":"https://www.wikidata.org/wiki/Q190411","display_name":"Field-programmable gate array","level":2,"score":0.20452848076820374}],"mesh":[],"locations_count":3,"locations":[{"id":"doi:10.1109/icecs.2015.7440313","is_oa":false,"landing_page_url":"https://doi.org/10.1109/icecs.2015.7440313","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2015 IEEE International Conference on Electronics, Circuits, and Systems (ICECS)","raw_type":"proceedings-article"},{"id":"pmh:oai:figshare.com:article/10144127","is_oa":true,"landing_page_url":"https://figshare.com/articles/conference_contribution/A_platform-based_design_framework_to_boost_many-core_software_development/10144127","pdf_url":null,"source":{"id":"https://openalex.org/S4377196282","display_name":"Figshare","issn_l":null,"issn":null,"is_oa":false,"is_in_doaj":false,"is_core":false,"host_organization":"https://openalex.org/I4210132348","host_organization_name":"Figshare (United Kingdom)","host_organization_lineage":["https://openalex.org/I4210132348"],"host_organization_lineage_names":[],"type":"repository"},"license":"cc-by","license_id":"https://openalex.org/licenses/cc-by","version":"submittedVersion","is_accepted":false,"is_published":false,"raw_source_name":"","raw_type":"Text"},{"id":"pmh:oai:lra.le.ac.uk:2381/37571","is_oa":true,"landing_page_url":"http://hdl.handle.net/2381/37571","pdf_url":null,"source":{"id":"https://openalex.org/S4306402365","display_name":"Leicester Research Archive (University of Leicester)","issn_l":null,"issn":null,"is_oa":false,"is_in_doaj":false,"is_core":false,"host_organization":"https://openalex.org/I153648349","host_organization_name":"University of Leicester","host_organization_lineage":["https://openalex.org/I153648349"],"host_organization_lineage_names":[],"type":"repository"},"license":"other-oa","license_id":"https://openalex.org/licenses/other-oa","version":"submittedVersion","is_accepted":false,"is_published":false,"raw_source_name":"","raw_type":"Conference Paper"}],"best_oa_location":{"id":"pmh:oai:figshare.com:article/10144127","is_oa":true,"landing_page_url":"https://figshare.com/articles/conference_contribution/A_platform-based_design_framework_to_boost_many-core_software_development/10144127","pdf_url":null,"source":{"id":"https://openalex.org/S4377196282","display_name":"Figshare","issn_l":null,"issn":null,"is_oa":false,"is_in_doaj":false,"is_core":false,"host_organization":"https://openalex.org/I4210132348","host_organization_name":"Figshare (United Kingdom)","host_organization_lineage":["https://openalex.org/I4210132348"],"host_organization_lineage_names":[],"type":"repository"},"license":"cc-by","license_id":"https://openalex.org/licenses/cc-by","version":"submittedVersion","is_accepted":false,"is_published":false,"raw_source_name":"","raw_type":"Text"},"sustainable_development_goals":[{"score":0.8899999856948853,"id":"https://metadata.un.org/sdg/7","display_name":"Affordable and clean energy"}],"awards":[],"funders":[{"id":"https://openalex.org/F4320322025","display_name":"Conselho Nacional de Desenvolvimento Cient\u00edfico e Tecnol\u00f3gico","ror":"https://ror.org/03swz6y49"}],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":15,"referenced_works":["https://openalex.org/W1989518382","https://openalex.org/W2002732892","https://openalex.org/W2022071403","https://openalex.org/W2043254158","https://openalex.org/W2046512977","https://openalex.org/W2054613700","https://openalex.org/W2089472638","https://openalex.org/W2092276663","https://openalex.org/W2100766117","https://openalex.org/W2147657366","https://openalex.org/W2164095419","https://openalex.org/W3144068561","https://openalex.org/W4256101352","https://openalex.org/W6662092935","https://openalex.org/W6681982535"],"related_works":["https://openalex.org/W3206586607","https://openalex.org/W2548514518","https://openalex.org/W2975035977","https://openalex.org/W2579932084","https://openalex.org/W2139939460","https://openalex.org/W2155040834","https://openalex.org/W2079291856","https://openalex.org/W2359630088","https://openalex.org/W1603163876","https://openalex.org/W2133642747"],"abstract_inverted_index":{"Embedded":[0],"software":[1,9,24,51,77,95],"engineers":[2],"are":[3],"dealing":[4],"with":[5],"complex":[6],"and":[7,23,45,80,97,109,141,167],"large":[8],"codes,":[10],"which":[11],"will":[12],"continue":[13],"to":[14,68,105,171],"grow.":[15],"To":[16],"achieve":[17],"a":[18],"cost-effective":[19],"design,":[20],"concomitant":[21],"hardware":[22],"development":[25],"is":[26,83,103],"required":[27],"during":[28],"early":[29],"design":[30,39],"phases.":[31],"This":[32],"paper":[33],"presents":[34,157],"an":[35],"open-source":[36],"platform":[37],"based":[38],"framework":[40],"that":[41],"combines":[42],"different":[43],"ADLs":[44],"simulators":[46],"aiming":[47],"at":[48],"improving":[49],"embedded":[50,56],"productivity,":[52],"targeting":[53],"future":[54],"many-core":[55],"systems.":[57],"The":[58,76,112,154],"proposed":[59,152],"approach":[60],"adopts":[61],"three":[62],"models:":[63],"RTL-VHDL":[64,177],"level;":[65],"RTL-SystemC":[66,165,169],"coupled":[67],"ISSs;":[69],"PBD":[70],"(Platform":[71],"Based":[72],"Design)":[73],"using":[74,150],"OVP.":[75],"(operating":[78],"system":[79],"user":[81],"applications)":[82],"the":[84,90,100,119,125,142,151,164,168,176],"same":[85],"for":[86,147],"both":[87],"models.":[88],"Therefore,":[89],"OVP":[91,155],"modeling":[92],"allows":[93],"fast":[94],"validation":[96,120],"debuggability.":[98],"With":[99],"SystemC-ISS,":[101],"it":[102],"possible":[104],"accurate":[106],"estimate":[107],"performance":[108],"energy":[110],"consumption.":[111],"low-level":[113,122],"model":[114,156],"enables,":[115],"besides":[116],"area":[117],"estimation,":[118],"of":[121,144],"protocols,":[123],"as":[124],"communication":[126],"protocol,":[127],"network":[128],"interface":[129],"or":[130],"flow-control":[131],"mechanisms":[132],"between":[133],"routers.":[134],"Results":[135],"evaluate":[136],"execution":[137],"time,":[138,140],"simulation":[139],"number":[143],"executed":[145],"instructions":[146],"several":[148],"benchmarks":[149],"approach.":[153],"in":[158],"average":[159],"five":[160],"times":[161,173],"faster":[162,174],"than":[163,175],"model,":[166],"up":[170],"155":[172],"model.":[178]},"counts_by_year":[{"year":2022,"cited_by_count":1},{"year":2021,"cited_by_count":1}],"updated_date":"2026-04-05T17:49:38.594831","created_date":"2025-10-10T00:00:00"}