{"id":"https://openalex.org/W2103746659","doi":"https://doi.org/10.1109/icecs.2009.5410779","title":"Layout exploration of geometrically accurate arithmetic circuits","display_name":"Layout exploration of geometrically accurate arithmetic circuits","publication_year":2009,"publication_date":"2009-12-01","ids":{"openalex":"https://openalex.org/W2103746659","doi":"https://doi.org/10.1109/icecs.2009.5410779","mag":"2103746659"},"language":"en","primary_location":{"id":"doi:10.1109/icecs.2009.5410779","is_oa":false,"landing_page_url":"https://doi.org/10.1109/icecs.2009.5410779","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2009 16th IEEE International Conference on Electronics, Circuits and Systems - (ICECS 2009)","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5056401853","display_name":"Kasyab P. Subramaniyan","orcid":null},"institutions":[{"id":"https://openalex.org/I66862912","display_name":"Chalmers University of Technology","ror":"https://ror.org/040wg7k59","country_code":"SE","type":"education","lineage":["https://openalex.org/I66862912"]}],"countries":["SE"],"is_corresponding":true,"raw_author_name":"Kasyab P Subramaniyan","raw_affiliation_strings":["Department of Computer Science and Engineering, Chalmers University of Technology, Gothenburg, Sweden","Department of Computer Science and Engineering, Chalmers University of Technology, SE-412 96 Gothenburg, Sweden;"],"affiliations":[{"raw_affiliation_string":"Department of Computer Science and Engineering, Chalmers University of Technology, Gothenburg, Sweden","institution_ids":["https://openalex.org/I66862912"]},{"raw_affiliation_string":"Department of Computer Science and Engineering, Chalmers University of Technology, SE-412 96 Gothenburg, Sweden;","institution_ids":["https://openalex.org/I66862912"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5022341974","display_name":"Emil Axelsson","orcid":"https://orcid.org/0000-0003-3482-6356"},"institutions":[{"id":"https://openalex.org/I66862912","display_name":"Chalmers University of Technology","ror":"https://ror.org/040wg7k59","country_code":"SE","type":"education","lineage":["https://openalex.org/I66862912"]}],"countries":["SE"],"is_corresponding":false,"raw_author_name":"Emil Axelsson","raw_affiliation_strings":["Department of Computer Science and Engineering, Chalmers University of Technology, Gothenburg, Sweden","Department of Computer Science and Engineering, Chalmers University of Technology, SE-412 96 Gothenburg, Sweden;"],"affiliations":[{"raw_affiliation_string":"Department of Computer Science and Engineering, Chalmers University of Technology, Gothenburg, Sweden","institution_ids":["https://openalex.org/I66862912"]},{"raw_affiliation_string":"Department of Computer Science and Engineering, Chalmers University of Technology, SE-412 96 Gothenburg, Sweden;","institution_ids":["https://openalex.org/I66862912"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5053343948","display_name":"Per Larsson-Edefors","orcid":"https://orcid.org/0000-0001-5779-4313"},"institutions":[{"id":"https://openalex.org/I66862912","display_name":"Chalmers University of Technology","ror":"https://ror.org/040wg7k59","country_code":"SE","type":"education","lineage":["https://openalex.org/I66862912"]}],"countries":["SE"],"is_corresponding":false,"raw_author_name":"Per Larsson-Edefors","raw_affiliation_strings":["Department of Computer Science and Engineering, Chalmers University of Technology, Gothenburg, Sweden","Department of Computer Science and Engineering, Chalmers University of Technology, SE-412 96 Gothenburg, Sweden;"],"affiliations":[{"raw_affiliation_string":"Department of Computer Science and Engineering, Chalmers University of Technology, Gothenburg, Sweden","institution_ids":["https://openalex.org/I66862912"]},{"raw_affiliation_string":"Department of Computer Science and Engineering, Chalmers University of Technology, SE-412 96 Gothenburg, Sweden;","institution_ids":["https://openalex.org/I66862912"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5037308838","display_name":"Mary Sheeran","orcid":"https://orcid.org/0000-0003-2509-0957"},"institutions":[{"id":"https://openalex.org/I66862912","display_name":"Chalmers University of Technology","ror":"https://ror.org/040wg7k59","country_code":"SE","type":"education","lineage":["https://openalex.org/I66862912"]}],"countries":["SE"],"is_corresponding":false,"raw_author_name":"Mary Sheeran","raw_affiliation_strings":["Department of Computer Science and Engineering, Chalmers University of Technology, Gothenburg, Sweden","Department of Computer Science and Engineering, Chalmers University of Technology, SE-412 96 Gothenburg, Sweden;"],"affiliations":[{"raw_affiliation_string":"Department of Computer Science and Engineering, Chalmers University of Technology, Gothenburg, Sweden","institution_ids":["https://openalex.org/I66862912"]},{"raw_affiliation_string":"Department of Computer Science and Engineering, Chalmers University of Technology, SE-412 96 Gothenburg, Sweden;","institution_ids":["https://openalex.org/I66862912"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":4,"corresponding_author_ids":["https://openalex.org/A5056401853"],"corresponding_institution_ids":["https://openalex.org/I66862912"],"apc_list":null,"apc_paid":null,"fwci":0.9137,"has_fulltext":false,"cited_by_count":4,"citation_normalized_percentile":{"value":0.77451454,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":89,"max":94},"biblio":{"volume":"34","issue":null,"first_page":"795","last_page":"798"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11522","display_name":"VLSI and FPGA Design Techniques","score":0.9997000098228455,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10558","display_name":"Advancements in Semiconductor Devices and Circuit Design","score":0.9987999796867371,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.7641487121582031},{"id":"https://openalex.org/keywords/electronic-circuit","display_name":"Electronic circuit","score":0.583299994468689},{"id":"https://openalex.org/keywords/arbitrary-precision-arithmetic","display_name":"Arbitrary-precision arithmetic","score":0.5593996047973633},{"id":"https://openalex.org/keywords/task","display_name":"Task (project management)","score":0.5533506870269775},{"id":"https://openalex.org/keywords/arithmetic","display_name":"Arithmetic","score":0.5184478163719177},{"id":"https://openalex.org/keywords/standard-cell","display_name":"Standard cell","score":0.5072824358940125},{"id":"https://openalex.org/keywords/computer-engineering","display_name":"Computer engineering","score":0.4764440655708313},{"id":"https://openalex.org/keywords/adder","display_name":"Adder","score":0.4509711265563965},{"id":"https://openalex.org/keywords/design-methods","display_name":"Design methods","score":0.4141216576099396},{"id":"https://openalex.org/keywords/computer-hardware","display_name":"Computer hardware","score":0.3776942193508148},{"id":"https://openalex.org/keywords/computer-architecture","display_name":"Computer architecture","score":0.34041646122932434},{"id":"https://openalex.org/keywords/integrated-circuit","display_name":"Integrated circuit","score":0.3139082193374634},{"id":"https://openalex.org/keywords/algorithm","display_name":"Algorithm","score":0.2594009041786194},{"id":"https://openalex.org/keywords/mathematics","display_name":"Mathematics","score":0.144056499004364},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.10643365979194641}],"concepts":[{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.7641487121582031},{"id":"https://openalex.org/C134146338","wikidata":"https://www.wikidata.org/wiki/Q1815901","display_name":"Electronic circuit","level":2,"score":0.583299994468689},{"id":"https://openalex.org/C83581934","wikidata":"https://www.wikidata.org/wiki/Q527381","display_name":"Arbitrary-precision arithmetic","level":2,"score":0.5593996047973633},{"id":"https://openalex.org/C2780451532","wikidata":"https://www.wikidata.org/wiki/Q759676","display_name":"Task (project management)","level":2,"score":0.5533506870269775},{"id":"https://openalex.org/C94375191","wikidata":"https://www.wikidata.org/wiki/Q11205","display_name":"Arithmetic","level":1,"score":0.5184478163719177},{"id":"https://openalex.org/C78401558","wikidata":"https://www.wikidata.org/wiki/Q464496","display_name":"Standard cell","level":3,"score":0.5072824358940125},{"id":"https://openalex.org/C113775141","wikidata":"https://www.wikidata.org/wiki/Q428691","display_name":"Computer engineering","level":1,"score":0.4764440655708313},{"id":"https://openalex.org/C164620267","wikidata":"https://www.wikidata.org/wiki/Q376953","display_name":"Adder","level":3,"score":0.4509711265563965},{"id":"https://openalex.org/C138852830","wikidata":"https://www.wikidata.org/wiki/Q2292993","display_name":"Design methods","level":2,"score":0.4141216576099396},{"id":"https://openalex.org/C9390403","wikidata":"https://www.wikidata.org/wiki/Q3966","display_name":"Computer hardware","level":1,"score":0.3776942193508148},{"id":"https://openalex.org/C118524514","wikidata":"https://www.wikidata.org/wiki/Q173212","display_name":"Computer architecture","level":1,"score":0.34041646122932434},{"id":"https://openalex.org/C530198007","wikidata":"https://www.wikidata.org/wiki/Q80831","display_name":"Integrated circuit","level":2,"score":0.3139082193374634},{"id":"https://openalex.org/C11413529","wikidata":"https://www.wikidata.org/wiki/Q8366","display_name":"Algorithm","level":1,"score":0.2594009041786194},{"id":"https://openalex.org/C33923547","wikidata":"https://www.wikidata.org/wiki/Q395","display_name":"Mathematics","level":0,"score":0.144056499004364},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.10643365979194641},{"id":"https://openalex.org/C119599485","wikidata":"https://www.wikidata.org/wiki/Q43035","display_name":"Electrical engineering","level":1,"score":0.0},{"id":"https://openalex.org/C201995342","wikidata":"https://www.wikidata.org/wiki/Q682496","display_name":"Systems engineering","level":1,"score":0.0},{"id":"https://openalex.org/C78519656","wikidata":"https://www.wikidata.org/wiki/Q101333","display_name":"Mechanical engineering","level":1,"score":0.0},{"id":"https://openalex.org/C111919701","wikidata":"https://www.wikidata.org/wiki/Q9135","display_name":"Operating system","level":1,"score":0.0},{"id":"https://openalex.org/C76155785","wikidata":"https://www.wikidata.org/wiki/Q418","display_name":"Telecommunications","level":1,"score":0.0},{"id":"https://openalex.org/C82876162","wikidata":"https://www.wikidata.org/wiki/Q17096504","display_name":"Latency (audio)","level":2,"score":0.0}],"mesh":[],"locations_count":3,"locations":[{"id":"doi:10.1109/icecs.2009.5410779","is_oa":false,"landing_page_url":"https://doi.org/10.1109/icecs.2009.5410779","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2009 16th IEEE International Conference on Electronics, Circuits and Systems - (ICECS 2009)","raw_type":"proceedings-article"},{"id":"pmh:oai:publications.lib.chalmers.se:102797","is_oa":false,"landing_page_url":"http://publications.lib.chalmers.se/publication/102797-layout-exploration-of-geometrically-accurate-arithmetic-circuits","pdf_url":null,"source":{"id":"https://openalex.org/S4377196470","display_name":"Chalmers Publication Library (Chalmers University of Technology)","issn_l":null,"issn":null,"is_oa":false,"is_in_doaj":false,"is_core":false,"host_organization":"https://openalex.org/I66862912","host_organization_name":"Chalmers University of Technology","host_organization_lineage":["https://openalex.org/I66862912"],"host_organization_lineage_names":[],"type":"repository"},"license":null,"license_id":null,"version":"submittedVersion","is_accepted":false,"is_published":false,"raw_source_name":"","raw_type":"Text.Article.Conference.PeerReviewed"},{"id":"pmh:oai:research.chalmers.se:102797","is_oa":false,"landing_page_url":"https://research.chalmers.se/en/publication/102797","pdf_url":null,"source":{"id":"https://openalex.org/S4306402469","display_name":"Chalmers Research (Chalmers University of Technology)","issn_l":null,"issn":null,"is_oa":false,"is_in_doaj":false,"is_core":false,"host_organization":"https://openalex.org/I66862912","host_organization_name":"Chalmers University of Technology","host_organization_lineage":["https://openalex.org/I66862912"],"host_organization_lineage_names":[],"type":"repository"},"license":null,"license_id":null,"version":"submittedVersion","is_accepted":false,"is_published":false,"raw_source_name":"","raw_type":""}],"best_oa_location":null,"sustainable_development_goals":[],"awards":[],"funders":[],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":8,"referenced_works":["https://openalex.org/W223847379","https://openalex.org/W1504785761","https://openalex.org/W1596988140","https://openalex.org/W1755575651","https://openalex.org/W1915608691","https://openalex.org/W1983849809","https://openalex.org/W2083811411","https://openalex.org/W2154098113"],"related_works":["https://openalex.org/W4390550886","https://openalex.org/W3217463396","https://openalex.org/W2790557758","https://openalex.org/W2516396101","https://openalex.org/W3204929712","https://openalex.org/W2059812140","https://openalex.org/W2610514210","https://openalex.org/W90892980","https://openalex.org/W2757604236","https://openalex.org/W2151657833"],"abstract_inverted_index":{"High-performance":[0],"arithmetic":[1,34],"circuits":[2,35],"are":[3,10],"critical":[4],"to":[5,32,68,91],"overall":[6,85],"design":[7,15,33],"performance":[8,42],"and":[9,22,71,76],"therefore":[11],"designed":[12,67],"using":[13,36],"full-custom":[14],"techniques.":[16],"However,":[17],"this":[18,101],"is":[19],"a":[20,27,60,108],"time-consuming":[21],"error-prone":[23],"task.":[24],"We":[25,99],"present":[26],"novel":[28],"layout":[29,112],"exploration":[30],"methodology":[31,102],"standard-cell":[37],"techniques,":[38],"that":[39,106],"retains":[40],"competitive":[41],"while":[43],"allowing":[44],"an":[45,56],"almost":[46],"custom-design":[47],"kind":[48],"of":[49,87,111],"control":[50],"over":[51],"the":[52,64,78,88],"layout.":[53],"It":[54],"uses":[55],"unconventional":[57],"approach":[58],"with":[59],"Haskell-based":[61],"front-end":[62],"in":[63],"Wired":[65],"system,":[66],"produce":[69],"logically":[70],"topologically":[72],"accurate":[73],"circuit":[74],"descriptions":[75],"at":[77],"same":[79],"time":[80,94],"be":[81],"parameterizable.":[82],"Further,":[83],"another":[84],"goal":[86],"system":[89],"was":[90],"keep":[92],"implementation":[93],"as":[95,97],"low":[96],"possible.":[98],"demonstrate":[100],"on":[103],"HPM":[104],"multipliers":[105],"exhibit":[107],"high":[109],"degree":[110],"regularity.":[113]},"counts_by_year":[{"year":2013,"cited_by_count":1},{"year":2012,"cited_by_count":1}],"updated_date":"2026-04-04T16:13:02.066488","created_date":"2025-10-10T00:00:00"}
