{"id":"https://openalex.org/W2096672269","doi":"https://doi.org/10.1109/icecs.2009.5410771","title":"Improved clock-phase generator based on self-biased CMOS logic for time-interleaved SC circuits","display_name":"Improved clock-phase generator based on self-biased CMOS logic for time-interleaved SC circuits","publication_year":2009,"publication_date":"2009-12-01","ids":{"openalex":"https://openalex.org/W2096672269","doi":"https://doi.org/10.1109/icecs.2009.5410771","mag":"2096672269"},"language":"en","primary_location":{"id":"doi:10.1109/icecs.2009.5410771","is_oa":false,"landing_page_url":"https://doi.org/10.1109/icecs.2009.5410771","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2009 16th IEEE International Conference on Electronics, Circuits and Systems - (ICECS 2009)","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5100676548","display_name":"M.M. Figueiredo","orcid":"https://orcid.org/0000-0002-2868-8332"},"institutions":[{"id":"https://openalex.org/I83558840","display_name":"Universidade Nova de Lisboa","ror":"https://ror.org/02xankh89","country_code":"PT","type":"education","lineage":["https://openalex.org/I83558840"]}],"countries":["PT"],"is_corresponding":true,"raw_author_name":"M. Figueiredo","raw_affiliation_strings":["Department of Electrical Engineering, Faculdade de Ci\u00eancias e Tecnologia (FCT), Universidade Nova de Lisboa, Monte da Caparica, Portugal"],"affiliations":[{"raw_affiliation_string":"Department of Electrical Engineering, Faculdade de Ci\u00eancias e Tecnologia (FCT), Universidade Nova de Lisboa, Monte da Caparica, Portugal","institution_ids":["https://openalex.org/I83558840"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5081085708","display_name":"T. Michalak","orcid":"https://orcid.org/0000-0002-2802-8051"},"institutions":[{"id":"https://openalex.org/I83558840","display_name":"Universidade Nova de Lisboa","ror":"https://ror.org/02xankh89","country_code":"PT","type":"education","lineage":["https://openalex.org/I83558840"]},{"id":"https://openalex.org/I46597724","display_name":"Pozna\u0144 University of Technology","ror":"https://ror.org/00p7p3302","country_code":"PL","type":"education","lineage":["https://openalex.org/I46597724"]}],"countries":["PL","PT"],"is_corresponding":false,"raw_author_name":"T. Michalak","raw_affiliation_strings":["Department of Electrical Engineering, Faculdade de Ci\u00eancias e Tecnologia (FCT), Universidade Nova de Lisboa, Monte da Caparica, Portugal","Faculty of Computing Science and Management, Chair of Computer Engineering, Poznan University of Technology, Poznan, Poland"],"affiliations":[{"raw_affiliation_string":"Department of Electrical Engineering, Faculdade de Ci\u00eancias e Tecnologia (FCT), Universidade Nova de Lisboa, Monte da Caparica, Portugal","institution_ids":["https://openalex.org/I83558840"]},{"raw_affiliation_string":"Faculty of Computing Science and Management, Chair of Computer Engineering, Poznan University of Technology, Poznan, Poland","institution_ids":["https://openalex.org/I46597724"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5035700004","display_name":"Jo\u00e3o Go\u00eas","orcid":"https://orcid.org/0000-0002-8434-8391"},"institutions":[{"id":"https://openalex.org/I83558840","display_name":"Universidade Nova de Lisboa","ror":"https://ror.org/02xankh89","country_code":"PT","type":"education","lineage":["https://openalex.org/I83558840"]}],"countries":["PT"],"is_corresponding":false,"raw_author_name":"J. Goes","raw_affiliation_strings":["Department of Electrical Engineering, Faculdade de Ci\u00eancias e Tecnologia (FCT), Universidade Nova de Lisboa, Monte da Caparica, Portugal"],"affiliations":[{"raw_affiliation_string":"Department of Electrical Engineering, Faculdade de Ci\u00eancias e Tecnologia (FCT), Universidade Nova de Lisboa, Monte da Caparica, Portugal","institution_ids":["https://openalex.org/I83558840"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5100738132","display_name":"L\u00fa\u0131s Gomes","orcid":"https://orcid.org/0000-0003-4299-8270"},"institutions":[{"id":"https://openalex.org/I83558840","display_name":"Universidade Nova de Lisboa","ror":"https://ror.org/02xankh89","country_code":"PT","type":"education","lineage":["https://openalex.org/I83558840"]}],"countries":["PT"],"is_corresponding":false,"raw_author_name":"L. Gomes","raw_affiliation_strings":["Department of Electrical Engineering, Faculdade de Ci\u00eancias e Tecnologia (FCT), Universidade Nova de Lisboa, Monte da Caparica, Portugal"],"affiliations":[{"raw_affiliation_string":"Department of Electrical Engineering, Faculdade de Ci\u00eancias e Tecnologia (FCT), Universidade Nova de Lisboa, Monte da Caparica, Portugal","institution_ids":["https://openalex.org/I83558840"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5043444372","display_name":"Pawe\u0142 \u015aniata\u0142a","orcid":"https://orcid.org/0000-0002-1792-8441"},"institutions":[{"id":"https://openalex.org/I46597724","display_name":"Pozna\u0144 University of Technology","ror":"https://ror.org/00p7p3302","country_code":"PL","type":"education","lineage":["https://openalex.org/I46597724"]}],"countries":["PL"],"is_corresponding":false,"raw_author_name":"P. Sniatala","raw_affiliation_strings":["Faculty of Computing Science and Management, Chair of Computer Engineering, Poznan University of Technology, Poznan, Poland"],"affiliations":[{"raw_affiliation_string":"Faculty of Computing Science and Management, Chair of Computer Engineering, Poznan University of Technology, Poznan, Poland","institution_ids":["https://openalex.org/I46597724"]}]}],"institutions":[],"countries_distinct_count":2,"institutions_distinct_count":5,"corresponding_author_ids":["https://openalex.org/A5100676548"],"corresponding_institution_ids":["https://openalex.org/I83558840"],"apc_list":null,"apc_paid":null,"fwci":0.2991,"has_fulltext":false,"cited_by_count":4,"citation_normalized_percentile":{"value":0.62996223,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":89,"max":96},"biblio":{"volume":"1","issue":null,"first_page":"763","last_page":"766"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T11417","display_name":"Advancements in PLL and VCO Technologies","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T11417","display_name":"Advancements in PLL and VCO Technologies","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10323","display_name":"Analog and Mixed-Signal Circuit Design","score":0.9986000061035156,"subfield":{"id":"https://openalex.org/subfields/2204","display_name":"Biomedical Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10187","display_name":"Radio Frequency Integrated Circuit Design","score":0.996999979019165,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/clock-generator","display_name":"Clock generator","score":0.8076155185699463},{"id":"https://openalex.org/keywords/clock-skew","display_name":"Clock skew","score":0.7315599918365479},{"id":"https://openalex.org/keywords/electronic-engineering","display_name":"Electronic engineering","score":0.5747027397155762},{"id":"https://openalex.org/keywords/cmos","display_name":"CMOS","score":0.5669911503791809},{"id":"https://openalex.org/keywords/skew","display_name":"Skew","score":0.5635184645652771},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.5596543550491333},{"id":"https://openalex.org/keywords/logic-gate","display_name":"Logic gate","score":0.5350692272186279},{"id":"https://openalex.org/keywords/digital-clock-manager","display_name":"Digital clock manager","score":0.5266245007514954},{"id":"https://openalex.org/keywords/clock-domain-crossing","display_name":"Clock domain crossing","score":0.47646546363830566},{"id":"https://openalex.org/keywords/clock-signal","display_name":"Clock signal","score":0.4754481017589569},{"id":"https://openalex.org/keywords/generator","display_name":"Generator (circuit theory)","score":0.47157755494117737},{"id":"https://openalex.org/keywords/electronic-circuit","display_name":"Electronic circuit","score":0.4528041183948517},{"id":"https://openalex.org/keywords/synchronous-circuit","display_name":"Synchronous circuit","score":0.444064199924469},{"id":"https://openalex.org/keywords/electrical-engineering","display_name":"Electrical engineering","score":0.35401248931884766},{"id":"https://openalex.org/keywords/power","display_name":"Power (physics)","score":0.35256829857826233},{"id":"https://openalex.org/keywords/jitter","display_name":"Jitter","score":0.33995386958122253},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.2177102267742157},{"id":"https://openalex.org/keywords/physics","display_name":"Physics","score":0.15628913044929504}],"concepts":[{"id":"https://openalex.org/C2778023540","wikidata":"https://www.wikidata.org/wiki/Q2164847","display_name":"Clock generator","level":4,"score":0.8076155185699463},{"id":"https://openalex.org/C60501442","wikidata":"https://www.wikidata.org/wiki/Q4382014","display_name":"Clock skew","level":4,"score":0.7315599918365479},{"id":"https://openalex.org/C24326235","wikidata":"https://www.wikidata.org/wiki/Q126095","display_name":"Electronic engineering","level":1,"score":0.5747027397155762},{"id":"https://openalex.org/C46362747","wikidata":"https://www.wikidata.org/wiki/Q173431","display_name":"CMOS","level":2,"score":0.5669911503791809},{"id":"https://openalex.org/C43711488","wikidata":"https://www.wikidata.org/wiki/Q7534783","display_name":"Skew","level":2,"score":0.5635184645652771},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.5596543550491333},{"id":"https://openalex.org/C131017901","wikidata":"https://www.wikidata.org/wiki/Q170451","display_name":"Logic gate","level":2,"score":0.5350692272186279},{"id":"https://openalex.org/C113074038","wikidata":"https://www.wikidata.org/wiki/Q5276052","display_name":"Digital clock manager","level":5,"score":0.5266245007514954},{"id":"https://openalex.org/C127204226","wikidata":"https://www.wikidata.org/wiki/Q5134799","display_name":"Clock domain crossing","level":5,"score":0.47646546363830566},{"id":"https://openalex.org/C137059387","wikidata":"https://www.wikidata.org/wiki/Q426882","display_name":"Clock signal","level":3,"score":0.4754481017589569},{"id":"https://openalex.org/C2780992000","wikidata":"https://www.wikidata.org/wiki/Q17016113","display_name":"Generator (circuit theory)","level":3,"score":0.47157755494117737},{"id":"https://openalex.org/C134146338","wikidata":"https://www.wikidata.org/wiki/Q1815901","display_name":"Electronic circuit","level":2,"score":0.4528041183948517},{"id":"https://openalex.org/C42196554","wikidata":"https://www.wikidata.org/wiki/Q1186179","display_name":"Synchronous circuit","level":4,"score":0.444064199924469},{"id":"https://openalex.org/C119599485","wikidata":"https://www.wikidata.org/wiki/Q43035","display_name":"Electrical engineering","level":1,"score":0.35401248931884766},{"id":"https://openalex.org/C163258240","wikidata":"https://www.wikidata.org/wiki/Q25342","display_name":"Power (physics)","level":2,"score":0.35256829857826233},{"id":"https://openalex.org/C134652429","wikidata":"https://www.wikidata.org/wiki/Q1052698","display_name":"Jitter","level":2,"score":0.33995386958122253},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.2177102267742157},{"id":"https://openalex.org/C121332964","wikidata":"https://www.wikidata.org/wiki/Q413","display_name":"Physics","level":0,"score":0.15628913044929504},{"id":"https://openalex.org/C62520636","wikidata":"https://www.wikidata.org/wiki/Q944","display_name":"Quantum mechanics","level":1,"score":0.0},{"id":"https://openalex.org/C76155785","wikidata":"https://www.wikidata.org/wiki/Q418","display_name":"Telecommunications","level":1,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/icecs.2009.5410771","is_oa":false,"landing_page_url":"https://doi.org/10.1109/icecs.2009.5410771","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2009 16th IEEE International Conference on Electronics, Circuits and Systems - (ICECS 2009)","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[{"id":"https://metadata.un.org/sdg/7","display_name":"Affordable and clean energy","score":0.7300000190734863}],"awards":[],"funders":[],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":11,"referenced_works":["https://openalex.org/W1580654973","https://openalex.org/W1824553993","https://openalex.org/W2095624237","https://openalex.org/W2109882734","https://openalex.org/W2114953806","https://openalex.org/W2129393153","https://openalex.org/W2171528701","https://openalex.org/W2216283733","https://openalex.org/W6634865859","https://openalex.org/W6638702932","https://openalex.org/W6674559331"],"related_works":["https://openalex.org/W2169622190","https://openalex.org/W2117541676","https://openalex.org/W2224788396","https://openalex.org/W2171851068","https://openalex.org/W2496244846","https://openalex.org/W2143420037","https://openalex.org/W2082030077","https://openalex.org/W1505287829","https://openalex.org/W2615366277","https://openalex.org/W44255833"],"abstract_inverted_index":{"This":[0],"paper":[1],"presents":[2],"an":[3,14,37],"improved":[4],"clock-phase":[5],"generator,":[6,60],"able":[7],"to":[8],"provide":[9],"two":[10],"non-overlapping":[11],"phases,":[12],"with":[13,42,55],"accurate":[15],"phase":[16],"shift":[17],"of":[18,28,70,93],"180":[19],"degrees.":[20],"The":[21],"circuit":[22,63,87],"relies":[23],"on":[24],"a":[25,65,75],"modified":[26],"version":[27],"the":[29,56,61,68,71,85],"classic":[30],"NAND-based":[31],"bi-phase":[32,58],"clock":[33,59],"generator":[34],"but":[35],"uses":[36],"equalizing":[38],"transmission":[39],"gate":[40],"together":[41],"dedicated":[43],"self-biased":[44],"logic.":[45],"Simulation":[46],"results":[47],"over":[48],"PVT":[49],"corners":[50],"show":[51],"that,":[52],"when":[53],"compared":[54],"original":[57],"proposed":[62,86],"exhibits":[64],"reduction":[66],"in":[67],"spread":[69],"phase-skew":[72],"error":[73],"by":[74],"factor":[76],"higher":[77],"than":[78],"2.4":[79],"whilst":[80],"dissipating":[81],"similar":[82],"power.":[83],"Moreover,":[84],"does":[88],"not":[89],"require":[90],"any":[91],"kind":[92],"calibration.":[94]},"counts_by_year":[{"year":2021,"cited_by_count":1},{"year":2014,"cited_by_count":2}],"updated_date":"2025-11-06T03:46:38.306776","created_date":"2025-10-10T00:00:00"}
