{"id":"https://openalex.org/W2538574317","doi":"https://doi.org/10.1109/icecs.2007.4511160","title":"An FPGA Implementation of a Scalable Network-on-Chip Based on the Token Ring Concept","display_name":"An FPGA Implementation of a Scalable Network-on-Chip Based on the Token Ring Concept","publication_year":2007,"publication_date":"2007-12-01","ids":{"openalex":"https://openalex.org/W2538574317","doi":"https://doi.org/10.1109/icecs.2007.4511160","mag":"2538574317"},"language":"en","primary_location":{"id":"doi:10.1109/icecs.2007.4511160","is_oa":false,"landing_page_url":"https://doi.org/10.1109/icecs.2007.4511160","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2007 14th IEEE International Conference on Electronics, Circuits and Systems","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5039765492","display_name":"K. Hadjiat","orcid":null},"institutions":[{"id":"https://openalex.org/I45683168","display_name":"Polytechnique Montr\u00e9al","ror":"https://ror.org/05f8d4e86","country_code":"CA","type":"education","lineage":["https://openalex.org/I45683168"]}],"countries":["CA"],"is_corresponding":true,"raw_author_name":"Karim Hadjiat","raw_affiliation_strings":["\u00c9cole Polytechnique de Montr\u00e9al, QC, Canada. karim.hadjiat@polymtl.ca","\u00c9cole Polytechnique de Montr\u00e9al, QUE, Canada"],"affiliations":[{"raw_affiliation_string":"\u00c9cole Polytechnique de Montr\u00e9al, QC, Canada. karim.hadjiat@polymtl.ca","institution_ids":["https://openalex.org/I45683168"]},{"raw_affiliation_string":"\u00c9cole Polytechnique de Montr\u00e9al, QUE, Canada","institution_ids":["https://openalex.org/I45683168"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5098426657","display_name":"Francis St-Pierre","orcid":null},"institutions":[{"id":"https://openalex.org/I45683168","display_name":"Polytechnique Montr\u00e9al","ror":"https://ror.org/05f8d4e86","country_code":"CA","type":"education","lineage":["https://openalex.org/I45683168"]}],"countries":["CA"],"is_corresponding":false,"raw_author_name":"Francis St-Pierre","raw_affiliation_strings":["\u00c9cole Polytechnique de Montr\u00e9al, QC, Canada. francis.stpierre@polymtl.ca","\u00c9cole Polytechnique de Montr\u00e9al, QUE, Canada"],"affiliations":[{"raw_affiliation_string":"\u00c9cole Polytechnique de Montr\u00e9al, QC, Canada. francis.stpierre@polymtl.ca","institution_ids":["https://openalex.org/I45683168"]},{"raw_affiliation_string":"\u00c9cole Polytechnique de Montr\u00e9al, QUE, Canada","institution_ids":["https://openalex.org/I45683168"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5019163790","display_name":"Guy Bois","orcid":"https://orcid.org/0000-0002-7595-9975"},"institutions":[{"id":"https://openalex.org/I45683168","display_name":"Polytechnique Montr\u00e9al","ror":"https://ror.org/05f8d4e86","country_code":"CA","type":"education","lineage":["https://openalex.org/I45683168"]}],"countries":["CA"],"is_corresponding":false,"raw_author_name":"Guy Bois","raw_affiliation_strings":["\u00c9cole Polytechnique de Montr\u00e9al, QC, Canada. guy.bois@polymtl.ca","\u00c9cole Polytechnique de Montr\u00e9al, QUE, Canada"],"affiliations":[{"raw_affiliation_string":"\u00c9cole Polytechnique de Montr\u00e9al, QC, Canada. guy.bois@polymtl.ca","institution_ids":["https://openalex.org/I45683168"]},{"raw_affiliation_string":"\u00c9cole Polytechnique de Montr\u00e9al, QUE, Canada","institution_ids":["https://openalex.org/I45683168"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5038488044","display_name":"Yvon Savaria","orcid":"https://orcid.org/0000-0002-3404-9959"},"institutions":[{"id":"https://openalex.org/I45683168","display_name":"Polytechnique Montr\u00e9al","ror":"https://ror.org/05f8d4e86","country_code":"CA","type":"education","lineage":["https://openalex.org/I45683168"]}],"countries":["CA"],"is_corresponding":false,"raw_author_name":"Yvon Savaria","raw_affiliation_strings":["\u00c9cole Polytechnique de Montr\u00e9al, QC, Canada. yvon.savaria@polymtl.ca","\u00c9cole Polytechnique de Montr\u00e9al, QUE, Canada"],"affiliations":[{"raw_affiliation_string":"\u00c9cole Polytechnique de Montr\u00e9al, QC, Canada. yvon.savaria@polymtl.ca","institution_ids":["https://openalex.org/I45683168"]},{"raw_affiliation_string":"\u00c9cole Polytechnique de Montr\u00e9al, QUE, Canada","institution_ids":["https://openalex.org/I45683168"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5024214334","display_name":"M. Langevin","orcid":null},"institutions":[],"countries":[],"is_corresponding":false,"raw_author_name":"Michel Langevin","raw_affiliation_strings":["STMicroelectronics, ON, Canada. michel.langevin@st.com","STMicroelectronics Group, ONT, Canada"],"affiliations":[{"raw_affiliation_string":"STMicroelectronics, ON, Canada. michel.langevin@st.com","institution_ids":[]},{"raw_affiliation_string":"STMicroelectronics Group, ONT, Canada","institution_ids":[]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5073518200","display_name":"Pierre Paulin","orcid":null},"institutions":[],"countries":[],"is_corresponding":false,"raw_author_name":"Pierre Paulin","raw_affiliation_strings":["STMicroelectronics, ON, Canada. pierre.paulin@st.com","STMicroelectronics Group, ONT, Canada"],"affiliations":[{"raw_affiliation_string":"STMicroelectronics, ON, Canada. pierre.paulin@st.com","institution_ids":[]},{"raw_affiliation_string":"STMicroelectronics Group, ONT, Canada","institution_ids":[]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":6,"corresponding_author_ids":["https://openalex.org/A5039765492"],"corresponding_institution_ids":["https://openalex.org/I45683168"],"apc_list":null,"apc_paid":null,"fwci":0.6771,"has_fulltext":false,"cited_by_count":5,"citation_normalized_percentile":{"value":0.77475456,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":90,"max":94},"biblio":{"volume":null,"issue":null,"first_page":"995","last_page":"998"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10829","display_name":"Interconnection Networks and Systems","score":1.0,"subfield":{"id":"https://openalex.org/subfields/1705","display_name":"Computer Networks and Communications"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10829","display_name":"Interconnection Networks and Systems","score":1.0,"subfield":{"id":"https://openalex.org/subfields/1705","display_name":"Computer Networks and Communications"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":0.9970999956130981,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10904","display_name":"Embedded Systems Design Techniques","score":0.9962999820709229,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/field-programmable-gate-array","display_name":"Field-programmable gate array","score":0.7849782705307007},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.7536313533782959},{"id":"https://openalex.org/keywords/scalability","display_name":"Scalability","score":0.7370679378509521},{"id":"https://openalex.org/keywords/security-token","display_name":"Security token","score":0.6158378720283508},{"id":"https://openalex.org/keywords/token-ring","display_name":"Token ring","score":0.5713217258453369},{"id":"https://openalex.org/keywords/bandwidth","display_name":"Bandwidth (computing)","score":0.571200966835022},{"id":"https://openalex.org/keywords/fpga-prototype","display_name":"FPGA prototype","score":0.47483187913894653},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.4706380069255829},{"id":"https://openalex.org/keywords/chip","display_name":"Chip","score":0.427554726600647},{"id":"https://openalex.org/keywords/computer-hardware","display_name":"Computer hardware","score":0.35341402888298035},{"id":"https://openalex.org/keywords/computer-network","display_name":"Computer network","score":0.3464210033416748},{"id":"https://openalex.org/keywords/operating-system","display_name":"Operating system","score":0.11364930868148804}],"concepts":[{"id":"https://openalex.org/C42935608","wikidata":"https://www.wikidata.org/wiki/Q190411","display_name":"Field-programmable gate array","level":2,"score":0.7849782705307007},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.7536313533782959},{"id":"https://openalex.org/C48044578","wikidata":"https://www.wikidata.org/wiki/Q727490","display_name":"Scalability","level":2,"score":0.7370679378509521},{"id":"https://openalex.org/C48145219","wikidata":"https://www.wikidata.org/wiki/Q1335365","display_name":"Security token","level":2,"score":0.6158378720283508},{"id":"https://openalex.org/C36653544","wikidata":"https://www.wikidata.org/wiki/Q207971","display_name":"Token ring","level":3,"score":0.5713217258453369},{"id":"https://openalex.org/C2776257435","wikidata":"https://www.wikidata.org/wiki/Q1576430","display_name":"Bandwidth (computing)","level":2,"score":0.571200966835022},{"id":"https://openalex.org/C203864433","wikidata":"https://www.wikidata.org/wiki/Q5426992","display_name":"FPGA prototype","level":3,"score":0.47483187913894653},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.4706380069255829},{"id":"https://openalex.org/C165005293","wikidata":"https://www.wikidata.org/wiki/Q1074500","display_name":"Chip","level":2,"score":0.427554726600647},{"id":"https://openalex.org/C9390403","wikidata":"https://www.wikidata.org/wiki/Q3966","display_name":"Computer hardware","level":1,"score":0.35341402888298035},{"id":"https://openalex.org/C31258907","wikidata":"https://www.wikidata.org/wiki/Q1301371","display_name":"Computer network","level":1,"score":0.3464210033416748},{"id":"https://openalex.org/C111919701","wikidata":"https://www.wikidata.org/wiki/Q9135","display_name":"Operating system","level":1,"score":0.11364930868148804},{"id":"https://openalex.org/C76155785","wikidata":"https://www.wikidata.org/wiki/Q418","display_name":"Telecommunications","level":1,"score":0.0}],"mesh":[],"locations_count":2,"locations":[{"id":"doi:10.1109/icecs.2007.4511160","is_oa":false,"landing_page_url":"https://doi.org/10.1109/icecs.2007.4511160","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2007 14th IEEE International Conference on Electronics, Circuits and Systems","raw_type":"proceedings-article"},{"id":"pmh:oai:publications.polymtl.ca:52728","is_oa":false,"landing_page_url":"https://publications.polymtl.ca/52728/","pdf_url":null,"source":{"id":"https://openalex.org/S4306401013","display_name":"PolyPublie (\u00c9cole Polytechnique de Montr\u00e9al)","issn_l":null,"issn":null,"is_oa":false,"is_in_doaj":false,"is_core":false,"host_organization":"https://openalex.org/I45683168","host_organization_name":"Polytechnique Montr\u00e9al","host_organization_lineage":["https://openalex.org/I45683168"],"host_organization_lineage_names":[],"type":"repository"},"license":null,"license_id":null,"version":"submittedVersion","is_accepted":false,"is_published":false,"raw_source_name":"","raw_type":"Communication de conf\u00e9rence"}],"best_oa_location":null,"sustainable_development_goals":[{"display_name":"Industry, innovation and infrastructure","score":0.49000000953674316,"id":"https://metadata.un.org/sdg/9"}],"awards":[],"funders":[],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":16,"referenced_works":["https://openalex.org/W1518438797","https://openalex.org/W1548168045","https://openalex.org/W1555458504","https://openalex.org/W2088943630","https://openalex.org/W2098038030","https://openalex.org/W2098156582","https://openalex.org/W2111978289","https://openalex.org/W2119677480","https://openalex.org/W2120538858","https://openalex.org/W2121856707","https://openalex.org/W2123184444","https://openalex.org/W2126213936","https://openalex.org/W2160642395","https://openalex.org/W2165666359","https://openalex.org/W6684387282","https://openalex.org/W6835467086"],"related_works":["https://openalex.org/W2102755122","https://openalex.org/W2136545404","https://openalex.org/W2118088052","https://openalex.org/W2057608425","https://openalex.org/W2074768958","https://openalex.org/W2142106817","https://openalex.org/W2998132311","https://openalex.org/W2106477326","https://openalex.org/W2397526281","https://openalex.org/W2207067480"],"abstract_inverted_index":{"In":[0],"this":[1],"paper,":[2],"we":[3],"present":[4],"an":[5,85],"FPGA":[6,117],"prototype":[7,27],"implementation":[8],"of":[9,36,57,81,88,95],"a":[10,13,46,60,73,77,116],"rotator-on-chip":[11],"(RoC),":[12],"simple":[14],"and":[15,38,113],"scalable":[16],"novel":[17],"network-on-chip":[18],"(NoC)":[19],"based":[20],"on":[21,72,115],"the":[22,34,55,82,93],"token-ring":[23],"concept.":[24],"The":[25,65],"reported":[26],"design":[28],"is":[29,68],"generic":[30],"with":[31,59],"respect":[32],"to":[33,101],"number":[35,56,94],"nodes":[37,79],"data":[39],"channels.":[40],"We":[41],"report":[42],"synthesis":[43],"results":[44],"showing":[45],"O(N":[47],"log":[48],"N)":[49],"area":[50,103],"complexity,":[51],"where":[52],"N":[53],"represents":[54],"nodes,":[58],"quasi-linear":[61],"aggregate":[62,86],"bandwidth":[63,87],"growth.":[64],"slice":[66],"utilization":[67],"less":[69],"than":[70],"25%":[71],"Xilinx":[74],"VP100":[75],"for":[76],"32":[78],"version":[80],"RoC,":[83],"supporting":[84],"about":[89],"12":[90],"GB/s.":[91],"Moreover,":[92],"channels":[96],"can":[97],"be":[98],"easily":[99],"configured":[100],"trade-off":[102],"versus":[104],"performance.":[105],"These":[106],"configurations":[107],"have":[108],"been":[109],"validated":[110],"by":[111],"simulation":[112],"implemented":[114],"development":[118],"board.":[119]},"counts_by_year":[{"year":2015,"cited_by_count":1}],"updated_date":"2026-03-20T20:47:17.329874","created_date":"2025-10-10T00:00:00"}
