{"id":"https://openalex.org/W2129095246","doi":"https://doi.org/10.1109/icecs.2007.4511095","title":"No-Handshake Asynchronous Survivor Memory Unit for a Viterbi Decoder","display_name":"No-Handshake Asynchronous Survivor Memory Unit for a Viterbi Decoder","publication_year":2007,"publication_date":"2007-12-01","ids":{"openalex":"https://openalex.org/W2129095246","doi":"https://doi.org/10.1109/icecs.2007.4511095","mag":"2129095246"},"language":"en","primary_location":{"id":"doi:10.1109/icecs.2007.4511095","is_oa":false,"landing_page_url":"https://doi.org/10.1109/icecs.2007.4511095","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2007 14th IEEE International Conference on Electronics, Circuits and Systems","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5083264630","display_name":"Wei Shao","orcid":"https://orcid.org/0000-0002-0663-6005"},"institutions":[{"id":"https://openalex.org/I28407311","display_name":"University of Manchester","ror":"https://ror.org/027m9bs27","country_code":"GB","type":"education","lineage":["https://openalex.org/I28407311"]}],"countries":["GB"],"is_corresponding":true,"raw_author_name":"Wei Shao","raw_affiliation_strings":["APT Group, School of Computer Science, University of Manchester, Oxford Road, UK","Univ. of Manchester, Oxford"],"affiliations":[{"raw_affiliation_string":"APT Group, School of Computer Science, University of Manchester, Oxford Road, UK","institution_ids":["https://openalex.org/I28407311"]},{"raw_affiliation_string":"Univ. of Manchester, Oxford","institution_ids":["https://openalex.org/I28407311"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5030853158","display_name":"L.E.M. Brackenbury","orcid":null},"institutions":[{"id":"https://openalex.org/I28407311","display_name":"University of Manchester","ror":"https://ror.org/027m9bs27","country_code":"GB","type":"education","lineage":["https://openalex.org/I28407311"]}],"countries":["GB"],"is_corresponding":false,"raw_author_name":"Linda Brackenbury","raw_affiliation_strings":["APT Group, School of Computer Science, University of Manchester, Oxford Road, UK","Univ. of Manchester, Oxford"],"affiliations":[{"raw_affiliation_string":"APT Group, School of Computer Science, University of Manchester, Oxford Road, UK","institution_ids":["https://openalex.org/I28407311"]},{"raw_affiliation_string":"Univ. of Manchester, Oxford","institution_ids":["https://openalex.org/I28407311"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":2,"corresponding_author_ids":["https://openalex.org/A5083264630"],"corresponding_institution_ids":["https://openalex.org/I28407311"],"apc_list":null,"apc_paid":null,"fwci":0.0,"has_fulltext":false,"cited_by_count":0,"citation_normalized_percentile":{"value":0.16132104,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":null,"biblio":{"volume":null,"issue":null,"first_page":"729","last_page":"734"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":0.9994000196456909,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":0.9994000196456909,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11321","display_name":"Error Correcting Code Techniques","score":0.9970999956130981,"subfield":{"id":"https://openalex.org/subfields/1705","display_name":"Computer Networks and Communications"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10829","display_name":"Interconnection Networks and Systems","score":0.9968000054359436,"subfield":{"id":"https://openalex.org/subfields/1705","display_name":"Computer Networks and Communications"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/handshaking","display_name":"Handshaking","score":0.8368266224861145},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.7871227860450745},{"id":"https://openalex.org/keywords/asynchronous-communication","display_name":"Asynchronous communication","score":0.7445600032806396},{"id":"https://openalex.org/keywords/handshake","display_name":"Handshake","score":0.7277485728263855},{"id":"https://openalex.org/keywords/viterbi-decoder","display_name":"Viterbi decoder","score":0.6993528604507446},{"id":"https://openalex.org/keywords/trace","display_name":"TRACE (psycholinguistics)","score":0.49082669615745544},{"id":"https://openalex.org/keywords/asynchronous-circuit","display_name":"Asynchronous circuit","score":0.48530668020248413},{"id":"https://openalex.org/keywords/microcode","display_name":"Microcode","score":0.4111776053905487},{"id":"https://openalex.org/keywords/computer-architecture","display_name":"Computer architecture","score":0.40872082114219666},{"id":"https://openalex.org/keywords/decoding-methods","display_name":"Decoding methods","score":0.39702939987182617},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.3726108968257904},{"id":"https://openalex.org/keywords/computer-hardware","display_name":"Computer hardware","score":0.3083905577659607},{"id":"https://openalex.org/keywords/computer-network","display_name":"Computer network","score":0.1561923623085022},{"id":"https://openalex.org/keywords/telecommunications","display_name":"Telecommunications","score":0.1065467894077301}],"concepts":[{"id":"https://openalex.org/C58861099","wikidata":"https://www.wikidata.org/wiki/Q548838","display_name":"Handshaking","level":2,"score":0.8368266224861145},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.7871227860450745},{"id":"https://openalex.org/C151319957","wikidata":"https://www.wikidata.org/wiki/Q752739","display_name":"Asynchronous communication","level":2,"score":0.7445600032806396},{"id":"https://openalex.org/C2778000800","wikidata":"https://www.wikidata.org/wiki/Q830043","display_name":"Handshake","level":3,"score":0.7277485728263855},{"id":"https://openalex.org/C117379686","wikidata":"https://www.wikidata.org/wiki/Q6996459","display_name":"Viterbi decoder","level":3,"score":0.6993528604507446},{"id":"https://openalex.org/C75291252","wikidata":"https://www.wikidata.org/wiki/Q1315756","display_name":"TRACE (psycholinguistics)","level":2,"score":0.49082669615745544},{"id":"https://openalex.org/C87695204","wikidata":"https://www.wikidata.org/wiki/Q629971","display_name":"Asynchronous circuit","level":5,"score":0.48530668020248413},{"id":"https://openalex.org/C22174128","wikidata":"https://www.wikidata.org/wiki/Q175869","display_name":"Microcode","level":2,"score":0.4111776053905487},{"id":"https://openalex.org/C118524514","wikidata":"https://www.wikidata.org/wiki/Q173212","display_name":"Computer architecture","level":1,"score":0.40872082114219666},{"id":"https://openalex.org/C57273362","wikidata":"https://www.wikidata.org/wiki/Q576722","display_name":"Decoding methods","level":2,"score":0.39702939987182617},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.3726108968257904},{"id":"https://openalex.org/C9390403","wikidata":"https://www.wikidata.org/wiki/Q3966","display_name":"Computer hardware","level":1,"score":0.3083905577659607},{"id":"https://openalex.org/C31258907","wikidata":"https://www.wikidata.org/wiki/Q1301371","display_name":"Computer network","level":1,"score":0.1561923623085022},{"id":"https://openalex.org/C76155785","wikidata":"https://www.wikidata.org/wiki/Q418","display_name":"Telecommunications","level":1,"score":0.1065467894077301},{"id":"https://openalex.org/C134652429","wikidata":"https://www.wikidata.org/wiki/Q1052698","display_name":"Jitter","level":2,"score":0.0},{"id":"https://openalex.org/C41895202","wikidata":"https://www.wikidata.org/wiki/Q8162","display_name":"Linguistics","level":1,"score":0.0},{"id":"https://openalex.org/C137059387","wikidata":"https://www.wikidata.org/wiki/Q426882","display_name":"Clock signal","level":3,"score":0.0},{"id":"https://openalex.org/C138885662","wikidata":"https://www.wikidata.org/wiki/Q5891","display_name":"Philosophy","level":0,"score":0.0},{"id":"https://openalex.org/C42196554","wikidata":"https://www.wikidata.org/wiki/Q1186179","display_name":"Synchronous circuit","level":4,"score":0.0}],"mesh":[],"locations_count":4,"locations":[{"id":"doi:10.1109/icecs.2007.4511095","is_oa":false,"landing_page_url":"https://doi.org/10.1109/icecs.2007.4511095","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2007 14th IEEE International Conference on Electronics, Circuits and Systems","raw_type":"proceedings-article"},{"id":"pmh:oai:CiteSeerX.psu:10.1.1.675.4109","is_oa":false,"landing_page_url":"http://citeseerx.ist.psu.edu/viewdoc/summary?doi=10.1.1.675.4109","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"submittedVersion","is_accepted":false,"is_published":false,"raw_source_name":"http://apt.cs.manchester.ac.uk/ftp/pub/apt/papers/WS_ICECS07.pdf","raw_type":"text"},{"id":"pmh:oai:pure.atira.dk:openaire_cris_publications/33ff93d2-66d8-4a33-a086-8fbe91ddcf39","is_oa":false,"landing_page_url":"https://research.manchester.ac.uk/en/publications/33ff93d2-66d8-4a33-a086-8fbe91ddcf39","pdf_url":null,"source":{"id":"https://openalex.org/S4306400662","display_name":"Research Explorer (The University of Manchester)","issn_l":null,"issn":null,"is_oa":false,"is_in_doaj":false,"is_core":false,"host_organization":"https://openalex.org/I28407311","host_organization_name":"University of Manchester","host_organization_lineage":["https://openalex.org/I28407311"],"host_organization_lineage_names":[],"type":"repository"},"license":null,"license_id":null,"version":"submittedVersion","is_accepted":false,"is_published":false,"raw_source_name":"Shao, W & Brackenbury, L 2007, No-handshake asynchronous survivor memory unit for a Viterbi decoder. in Proceedings of the IEEE International Conference on Electronics, Circuits, and Systems|Proc IEEE Int Conf Electron Circuits Syst. IEEE, pp. 729-734, 14th IEEE International Conference on Electronics, Circuits and Systems, ICECS 2007, Marrakech, 1/07/07. https://doi.org/10.1109/ICECS.2007.4511095","raw_type":"info:eu-repo/semantics/conferenceObject"},{"id":"pmh:oai:pure.atira.dk:publications/33ff93d2-66d8-4a33-a086-8fbe91ddcf39","is_oa":false,"landing_page_url":"https://www.research.manchester.ac.uk/portal/en/publications/nohandshake-asynchronous-survivor-memory-unit-for-a-viterbi-decoder(33ff93d2-66d8-4a33-a086-8fbe91ddcf39).html","pdf_url":null,"source":{"id":"https://openalex.org/S4306400662","display_name":"Research Explorer (The University of Manchester)","issn_l":null,"issn":null,"is_oa":false,"is_in_doaj":false,"is_core":false,"host_organization":"https://openalex.org/I28407311","host_organization_name":"University of Manchester","host_organization_lineage":["https://openalex.org/I28407311"],"host_organization_lineage_names":[],"type":"repository"},"license":null,"license_id":null,"version":"submittedVersion","is_accepted":false,"is_published":false,"raw_source_name":"Shao, W & Brackenbury, L 2007, No-handshake asynchronous survivor memory unit for a Viterbi decoder. in Proceedings of the IEEE International Conference on Electronics, Circuits, and Systems|Proc IEEE Int Conf Electron Circuits Syst. IEEE, pp. 729-734, 14th IEEE International Conference on Electronics, Circuits and Systems, ICECS 2007, Marrakech, 1/07/07. https://doi.org/10.1109/ICECS.2007.4511095","raw_type":"info:eu-repo/semantics/conferenceObject"}],"best_oa_location":null,"sustainable_development_goals":[],"awards":[],"funders":[{"id":"https://openalex.org/F4320334627","display_name":"Engineering and Physical Sciences Research Council","ror":"https://ror.org/0439y7842"}],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":6,"referenced_works":["https://openalex.org/W1614137482","https://openalex.org/W1836967236","https://openalex.org/W2006389550","https://openalex.org/W2089905389","https://openalex.org/W2161690309","https://openalex.org/W4242536966"],"related_works":["https://openalex.org/W2347296673","https://openalex.org/W2521973011","https://openalex.org/W2036690923","https://openalex.org/W2066480039","https://openalex.org/W2061563403","https://openalex.org/W2019002109","https://openalex.org/W3163080401","https://openalex.org/W2576660463","https://openalex.org/W4388007616","https://openalex.org/W344978372"],"abstract_inverted_index":{"The":[0,73],"survivor":[1],"memory":[2],"unit":[3],"(SMU)":[4],"is":[5,39,81],"a":[6,10,35,44,62,82,92,109,114,123],"vital":[7],"part":[8],"of":[9,18,47,103],"Viterbi":[11],"decoder":[12],"design.":[13,126],"So":[14],"far,":[15],"classical":[16],"implementations":[17],"SMU":[19,52,74,111],"employ":[20],"the":[21,25,30,51,69,96,104],"register":[22],"exchange":[23],"or":[24],"trace":[26,32,70],"back":[27,33,71],"approaches.":[28],"In":[29],"conventional":[31],"implementation,":[34],"read-write":[36],"RAM":[37],"architecture":[38,80,98],"generally":[40],"adopted":[41],"which":[42],"requires":[43],"large":[45],"size":[46],"memory.":[48],"This":[49,59],"gives":[50],"design":[53,75,112],"both":[54],"area":[55],"and":[56,85,119],"power":[57,105,116],"overhead.":[58],"paper":[60],"presents":[61],"new":[63,79,97],"no-handshake":[64],"asynchronous":[65,86,125],"approach":[66],"to":[67],"implement":[68],"method.":[72],"based":[76],"on":[77,91],"this":[78],"mixed":[83],"synchronous":[84],"circuit.":[87],"Post-layout":[88],"simulation":[89],"results":[90],"0.18\u03bcm":[93],"process":[94],"show":[95],"saves":[99],"more":[100],"than":[101],"84%":[102],"dissipated":[106],"compare":[107],"with":[108,122],"synchronised":[110],"using":[113],"low":[115],"logic":[117],"family":[118],"30%":[120],"compared":[121],"handshaking":[124]},"counts_by_year":[],"updated_date":"2026-04-05T17:49:38.594831","created_date":"2025-10-10T00:00:00"}
