{"id":"https://openalex.org/W2161964000","doi":"https://doi.org/10.1109/icecs.2007.4510953","title":"Datapath Delay Distributions for Data/Instruction against PVT Variations in 90nm CMOS","display_name":"Datapath Delay Distributions for Data/Instruction against PVT Variations in 90nm CMOS","publication_year":2007,"publication_date":"2007-12-01","ids":{"openalex":"https://openalex.org/W2161964000","doi":"https://doi.org/10.1109/icecs.2007.4510953","mag":"2161964000"},"language":"en","primary_location":{"id":"doi:10.1109/icecs.2007.4510953","is_oa":false,"landing_page_url":"https://doi.org/10.1109/icecs.2007.4510953","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2007 14th IEEE International Conference on Electronics, Circuits and Systems","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5102900006","display_name":"Makoto Ikeda","orcid":"https://orcid.org/0000-0002-6644-4224"},"institutions":[{"id":"https://openalex.org/I74801974","display_name":"The University of Tokyo","ror":"https://ror.org/057zh3y96","country_code":"JP","type":"education","lineage":["https://openalex.org/I74801974"]}],"countries":["JP"],"is_corresponding":true,"raw_author_name":"Makoto Ikeda","raw_affiliation_strings":["VLSI Design and Education Center, University of Tokyo, Tokyo, Japan. ikeda@silicon.u-tokyo.ac.jp","VLSI Design and Education Center, University of Tokyo, Tokyo, Japan"],"affiliations":[{"raw_affiliation_string":"VLSI Design and Education Center, University of Tokyo, Tokyo, Japan. ikeda@silicon.u-tokyo.ac.jp","institution_ids":["https://openalex.org/I74801974"]},{"raw_affiliation_string":"VLSI Design and Education Center, University of Tokyo, Tokyo, Japan","institution_ids":["https://openalex.org/I74801974"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5035563205","display_name":"K. Ishii","orcid":"https://orcid.org/0000-0003-0027-7141"},"institutions":[{"id":"https://openalex.org/I74801974","display_name":"The University of Tokyo","ror":"https://ror.org/057zh3y96","country_code":"JP","type":"education","lineage":["https://openalex.org/I74801974"]}],"countries":["JP"],"is_corresponding":false,"raw_author_name":"Ken Ishii","raw_affiliation_strings":["VLSI Design and Education Center, University of Tokyo, Tokyo, Japan"],"affiliations":[{"raw_affiliation_string":"VLSI Design and Education Center, University of Tokyo, Tokyo, Japan","institution_ids":["https://openalex.org/I74801974"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5109248106","display_name":"Taku Sogabe","orcid":null},"institutions":[{"id":"https://openalex.org/I4210122684","display_name":"Sony Computer Science Laboratories","ror":"https://ror.org/02nc46417","country_code":"JP","type":"facility","lineage":["https://openalex.org/I4210122684"]},{"id":"https://openalex.org/I74801974","display_name":"The University of Tokyo","ror":"https://ror.org/057zh3y96","country_code":"JP","type":"education","lineage":["https://openalex.org/I74801974"]}],"countries":["JP"],"is_corresponding":false,"raw_author_name":"Taku Sogabe","raw_affiliation_strings":["VLSI Design and Education Center, University of Tokyo, Tokyo, Japan. sogabe@silicon.u-tokyo.ac.jp","VLSI Design and Education Center, University of Tokyo, Tokyo, Japan"],"affiliations":[{"raw_affiliation_string":"VLSI Design and Education Center, University of Tokyo, Tokyo, Japan. sogabe@silicon.u-tokyo.ac.jp","institution_ids":["https://openalex.org/I4210122684"]},{"raw_affiliation_string":"VLSI Design and Education Center, University of Tokyo, Tokyo, Japan","institution_ids":["https://openalex.org/I74801974"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5102259024","display_name":"Kunihiro Asada","orcid":null},"institutions":[{"id":"https://openalex.org/I74801974","display_name":"The University of Tokyo","ror":"https://ror.org/057zh3y96","country_code":"JP","type":"education","lineage":["https://openalex.org/I74801974"]}],"countries":["JP"],"is_corresponding":false,"raw_author_name":"Kunihiro Asada","raw_affiliation_strings":["VLSI Design and Education Center, University of Tokyo, Tokyo, Japan. asada@silicon.u-tokyo.ac.jp","VLSI Design and Education Center, University of Tokyo, Tokyo, Japan"],"affiliations":[{"raw_affiliation_string":"VLSI Design and Education Center, University of Tokyo, Tokyo, Japan. asada@silicon.u-tokyo.ac.jp","institution_ids":["https://openalex.org/I74801974"]},{"raw_affiliation_string":"VLSI Design and Education Center, University of Tokyo, Tokyo, Japan","institution_ids":["https://openalex.org/I74801974"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":4,"corresponding_author_ids":["https://openalex.org/A5102900006"],"corresponding_institution_ids":["https://openalex.org/I74801974"],"apc_list":null,"apc_paid":null,"fwci":0.0,"has_fulltext":false,"cited_by_count":3,"citation_normalized_percentile":{"value":0.18019924,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":89,"max":94},"biblio":{"volume":null,"issue":null,"first_page":"154","last_page":"157"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10323","display_name":"Analog and Mixed-Signal Circuit Design","score":0.9993000030517578,"subfield":{"id":"https://openalex.org/subfields/2204","display_name":"Biomedical Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11005","display_name":"Radiation Effects in Electronics","score":0.9991000294685364,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/datapath","display_name":"Datapath","score":0.9847822189331055},{"id":"https://openalex.org/keywords/cmos","display_name":"CMOS","score":0.7673355340957642},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.5555998086929321},{"id":"https://openalex.org/keywords/electronic-engineering","display_name":"Electronic engineering","score":0.45387569069862366},{"id":"https://openalex.org/keywords/logic-synthesis","display_name":"Logic synthesis","score":0.449943482875824},{"id":"https://openalex.org/keywords/logic-gate","display_name":"Logic gate","score":0.4259645342826843},{"id":"https://openalex.org/keywords/process-variation","display_name":"Process variation","score":0.4247959852218628},{"id":"https://openalex.org/keywords/process","display_name":"Process (computing)","score":0.34579533338546753},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.2799839973449707},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.17008811235427856},{"id":"https://openalex.org/keywords/algorithm","display_name":"Algorithm","score":0.1349853277206421}],"concepts":[{"id":"https://openalex.org/C2781198647","wikidata":"https://www.wikidata.org/wiki/Q1633673","display_name":"Datapath","level":2,"score":0.9847822189331055},{"id":"https://openalex.org/C46362747","wikidata":"https://www.wikidata.org/wiki/Q173431","display_name":"CMOS","level":2,"score":0.7673355340957642},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.5555998086929321},{"id":"https://openalex.org/C24326235","wikidata":"https://www.wikidata.org/wiki/Q126095","display_name":"Electronic engineering","level":1,"score":0.45387569069862366},{"id":"https://openalex.org/C157922185","wikidata":"https://www.wikidata.org/wiki/Q173198","display_name":"Logic synthesis","level":3,"score":0.449943482875824},{"id":"https://openalex.org/C131017901","wikidata":"https://www.wikidata.org/wiki/Q170451","display_name":"Logic gate","level":2,"score":0.4259645342826843},{"id":"https://openalex.org/C93389723","wikidata":"https://www.wikidata.org/wiki/Q7247313","display_name":"Process variation","level":3,"score":0.4247959852218628},{"id":"https://openalex.org/C98045186","wikidata":"https://www.wikidata.org/wiki/Q205663","display_name":"Process (computing)","level":2,"score":0.34579533338546753},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.2799839973449707},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.17008811235427856},{"id":"https://openalex.org/C11413529","wikidata":"https://www.wikidata.org/wiki/Q8366","display_name":"Algorithm","level":1,"score":0.1349853277206421},{"id":"https://openalex.org/C111919701","wikidata":"https://www.wikidata.org/wiki/Q9135","display_name":"Operating system","level":1,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/icecs.2007.4510953","is_oa":false,"landing_page_url":"https://doi.org/10.1109/icecs.2007.4510953","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2007 14th IEEE International Conference on Electronics, Circuits and Systems","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[],"awards":[],"funders":[],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":6,"referenced_works":["https://openalex.org/W2000260960","https://openalex.org/W2069217703","https://openalex.org/W2086447087","https://openalex.org/W2100759575","https://openalex.org/W2117956094","https://openalex.org/W4238765112"],"related_works":["https://openalex.org/W2119748374","https://openalex.org/W2170979950","https://openalex.org/W1900707063","https://openalex.org/W2114514951","https://openalex.org/W1972393920","https://openalex.org/W1996820488","https://openalex.org/W2098419840","https://openalex.org/W1966764473","https://openalex.org/W2789349722","https://openalex.org/W1985308002"],"abstract_inverted_index":{"This":[0],"paper":[1],"presents":[2],"measurement":[3],"results":[4,59],"on":[5],"datapath":[6],"delay":[7,23,74],"distributions":[8],"for":[9,46,81,88],"data/instruction":[10],"against":[11,76],"Process,":[12],"Voltage":[13],"and":[14,43,49,69],"Temperature":[15,50],"(PVT)":[16],"variations":[17],"in":[18,66],"90":[19,82],"nm":[20,83],"CMOS.":[21,91],"Datapath":[22],"has":[24],"been":[25],"measured":[26],"using":[27],"a":[28],"completion":[29],"signal":[30],"generated":[31],"at":[32],"the":[33,63,72],"end":[34],"of":[35],"datapaths":[36],"with":[37,62],"dual-rail":[38],"logic":[39],"according":[40],"to":[41,54],"data":[42],"instructions":[44],"comprehensively":[45],"multiple":[47],"Vdd":[48],"among":[51],"several":[52],"chips":[53],"show":[55],"PVT":[56,77],"variations.":[57],"Measurement":[58],"were":[60],"compared":[61],"equivalent":[64],"design":[65],"0.35":[67,89],"um":[68],"demonstrated":[70],"that":[71,85],"average":[73],"variation":[75,78],"was":[79,86],"16%":[80],"where":[84],"10%":[87],"mum":[90]},"counts_by_year":[{"year":2019,"cited_by_count":1},{"year":2015,"cited_by_count":1},{"year":2013,"cited_by_count":1}],"updated_date":"2026-03-20T20:47:17.329874","created_date":"2025-10-10T00:00:00"}