{"id":"https://openalex.org/W2170435249","doi":"https://doi.org/10.1109/icecs.2007.4510922","title":"Low-Gain-Wide-Range 2.4-GHz Phase Locked Loop","display_name":"Low-Gain-Wide-Range 2.4-GHz Phase Locked Loop","publication_year":2007,"publication_date":"2007-12-01","ids":{"openalex":"https://openalex.org/W2170435249","doi":"https://doi.org/10.1109/icecs.2007.4510922","mag":"2170435249"},"language":"en","primary_location":{"id":"doi:10.1109/icecs.2007.4510922","is_oa":false,"landing_page_url":"https://doi.org/10.1109/icecs.2007.4510922","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2007 14th IEEE International Conference on Electronics, Circuits and Systems","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5040987810","display_name":"Wenceslas Rahajandraibe","orcid":"https://orcid.org/0000-0003-1508-5927"},"institutions":[{"id":"https://openalex.org/I1294671590","display_name":"Centre National de la Recherche Scientifique","ror":"https://ror.org/02feahw73","country_code":"FR","type":"government","lineage":["https://openalex.org/I1294671590"]},{"id":"https://openalex.org/I21491767","display_name":"Aix-Marseille Universit\u00e9","ror":"https://ror.org/035xkbk20","country_code":"FR","type":"education","lineage":["https://openalex.org/I21491767"]},{"id":"https://openalex.org/I4210152149","display_name":"Laboratoire de M\u00e9canique et Proc\u00e9d\u00e9s de Fabrication","ror":"https://ror.org/04yzbzc51","country_code":"FR","type":"facility","lineage":["https://openalex.org/I190752583","https://openalex.org/I190861549","https://openalex.org/I4210134562","https://openalex.org/I4210152149"]}],"countries":["FR"],"is_corresponding":true,"raw_author_name":"W. Rahajandraibe","raw_affiliation_strings":["L2MP - University of Provence UMR-CNRS 6137, Marseille, France. e-mail: wenceslas.rahajandraibe@l2mp.fr","L2MP-University of Provence UMR-CNRS 6137, Marseilles, France"],"affiliations":[{"raw_affiliation_string":"L2MP - University of Provence UMR-CNRS 6137, Marseille, France. e-mail: wenceslas.rahajandraibe@l2mp.fr","institution_ids":["https://openalex.org/I4210152149","https://openalex.org/I1294671590"]},{"raw_affiliation_string":"L2MP-University of Provence UMR-CNRS 6137, Marseilles, France","institution_ids":["https://openalex.org/I21491767","https://openalex.org/I1294671590"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5111923205","display_name":"L. Za\u00efd","orcid":null},"institutions":[{"id":"https://openalex.org/I1294671590","display_name":"Centre National de la Recherche Scientifique","ror":"https://ror.org/02feahw73","country_code":"FR","type":"government","lineage":["https://openalex.org/I1294671590"]},{"id":"https://openalex.org/I21491767","display_name":"Aix-Marseille Universit\u00e9","ror":"https://ror.org/035xkbk20","country_code":"FR","type":"education","lineage":["https://openalex.org/I21491767"]}],"countries":["FR"],"is_corresponding":false,"raw_author_name":"L. Zaid","raw_affiliation_strings":["L2MP - University of Provence UMR-CNRS 6137, Marseille, France","L2MP-University of Provence UMR-CNRS 6137, Marseilles, France"],"affiliations":[{"raw_affiliation_string":"L2MP - University of Provence UMR-CNRS 6137, Marseille, France","institution_ids":["https://openalex.org/I1294671590","https://openalex.org/I21491767"]},{"raw_affiliation_string":"L2MP-University of Provence UMR-CNRS 6137, Marseilles, France","institution_ids":["https://openalex.org/I21491767","https://openalex.org/I1294671590"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5033662832","display_name":"V. Cheynet de Beaupre","orcid":null},"institutions":[{"id":"https://openalex.org/I1294671590","display_name":"Centre National de la Recherche Scientifique","ror":"https://ror.org/02feahw73","country_code":"FR","type":"government","lineage":["https://openalex.org/I1294671590"]},{"id":"https://openalex.org/I21491767","display_name":"Aix-Marseille Universit\u00e9","ror":"https://ror.org/035xkbk20","country_code":"FR","type":"education","lineage":["https://openalex.org/I21491767"]}],"countries":["FR"],"is_corresponding":false,"raw_author_name":"V. Cheynet de Beaupre","raw_affiliation_strings":["L2MP - University of Provence UMR-CNRS 6137, Marseille, France","L2MP-University of Provence UMR-CNRS 6137, Marseilles, France"],"affiliations":[{"raw_affiliation_string":"L2MP - University of Provence UMR-CNRS 6137, Marseille, France","institution_ids":["https://openalex.org/I1294671590","https://openalex.org/I21491767"]},{"raw_affiliation_string":"L2MP-University of Provence UMR-CNRS 6137, Marseilles, France","institution_ids":["https://openalex.org/I21491767","https://openalex.org/I1294671590"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5084148161","display_name":"Julien Roche","orcid":null},"institutions":[{"id":"https://openalex.org/I1294671590","display_name":"Centre National de la Recherche Scientifique","ror":"https://ror.org/02feahw73","country_code":"FR","type":"government","lineage":["https://openalex.org/I1294671590"]},{"id":"https://openalex.org/I21491767","display_name":"Aix-Marseille Universit\u00e9","ror":"https://ror.org/035xkbk20","country_code":"FR","type":"education","lineage":["https://openalex.org/I21491767"]}],"countries":["FR"],"is_corresponding":false,"raw_author_name":"J. Roche","raw_affiliation_strings":["L2MP - University of Provence UMR-CNRS 6137, Marseille, France","L2MP-University of Provence UMR-CNRS 6137, Marseilles, France"],"affiliations":[{"raw_affiliation_string":"L2MP - University of Provence UMR-CNRS 6137, Marseille, France","institution_ids":["https://openalex.org/I1294671590","https://openalex.org/I21491767"]},{"raw_affiliation_string":"L2MP-University of Provence UMR-CNRS 6137, Marseilles, France","institution_ids":["https://openalex.org/I21491767","https://openalex.org/I1294671590"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":4,"corresponding_author_ids":["https://openalex.org/A5040987810"],"corresponding_institution_ids":["https://openalex.org/I1294671590","https://openalex.org/I21491767","https://openalex.org/I4210152149"],"apc_list":null,"apc_paid":null,"fwci":0.0,"has_fulltext":false,"cited_by_count":6,"citation_normalized_percentile":{"value":0.18525713,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":89,"max":96},"biblio":{"volume":null,"issue":null,"first_page":"26","last_page":"29"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T11417","display_name":"Advancements in PLL and VCO Technologies","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T11417","display_name":"Advancements in PLL and VCO Technologies","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10187","display_name":"Radio Frequency Integrated Circuit Design","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10323","display_name":"Analog and Mixed-Signal Circuit Design","score":0.9991000294685364,"subfield":{"id":"https://openalex.org/subfields/2204","display_name":"Biomedical Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/phase-noise","display_name":"Phase noise","score":0.8581584692001343},{"id":"https://openalex.org/keywords/phase-locked-loop","display_name":"Phase-locked loop","score":0.8349472284317017},{"id":"https://openalex.org/keywords/dbc","display_name":"dBc","score":0.8047455549240112},{"id":"https://openalex.org/keywords/delay-locked-loop","display_name":"Delay-locked loop","score":0.6918801069259644},{"id":"https://openalex.org/keywords/offset","display_name":"Offset (computer science)","score":0.5700092315673828},{"id":"https://openalex.org/keywords/cmos","display_name":"CMOS","score":0.5683212876319885},{"id":"https://openalex.org/keywords/loop","display_name":"Loop (graph theory)","score":0.4998917579650879},{"id":"https://openalex.org/keywords/electronic-engineering","display_name":"Electronic engineering","score":0.4985771179199219},{"id":"https://openalex.org/keywords/voltage-controlled-oscillator","display_name":"Voltage-controlled oscillator","score":0.4586738049983978},{"id":"https://openalex.org/keywords/loop-gain","display_name":"Loop gain","score":0.42971259355545044},{"id":"https://openalex.org/keywords/pll-multibit","display_name":"PLL multibit","score":0.4278544783592224},{"id":"https://openalex.org/keywords/electrical-engineering","display_name":"Electrical engineering","score":0.4078006148338318},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.3748597502708435},{"id":"https://openalex.org/keywords/voltage","display_name":"Voltage","score":0.3573257029056549},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.28395378589630127}],"concepts":[{"id":"https://openalex.org/C89631360","wikidata":"https://www.wikidata.org/wiki/Q1428766","display_name":"Phase noise","level":2,"score":0.8581584692001343},{"id":"https://openalex.org/C12707504","wikidata":"https://www.wikidata.org/wiki/Q52637","display_name":"Phase-locked loop","level":3,"score":0.8349472284317017},{"id":"https://openalex.org/C193523891","wikidata":"https://www.wikidata.org/wiki/Q1771950","display_name":"dBc","level":3,"score":0.8047455549240112},{"id":"https://openalex.org/C190462668","wikidata":"https://www.wikidata.org/wiki/Q492265","display_name":"Delay-locked loop","level":4,"score":0.6918801069259644},{"id":"https://openalex.org/C175291020","wikidata":"https://www.wikidata.org/wiki/Q1156822","display_name":"Offset (computer science)","level":2,"score":0.5700092315673828},{"id":"https://openalex.org/C46362747","wikidata":"https://www.wikidata.org/wiki/Q173431","display_name":"CMOS","level":2,"score":0.5683212876319885},{"id":"https://openalex.org/C184670325","wikidata":"https://www.wikidata.org/wiki/Q512604","display_name":"Loop (graph theory)","level":2,"score":0.4998917579650879},{"id":"https://openalex.org/C24326235","wikidata":"https://www.wikidata.org/wiki/Q126095","display_name":"Electronic engineering","level":1,"score":0.4985771179199219},{"id":"https://openalex.org/C5291336","wikidata":"https://www.wikidata.org/wiki/Q852341","display_name":"Voltage-controlled oscillator","level":3,"score":0.4586738049983978},{"id":"https://openalex.org/C199943209","wikidata":"https://www.wikidata.org/wiki/Q1271153","display_name":"Loop gain","level":3,"score":0.42971259355545044},{"id":"https://openalex.org/C77881186","wikidata":"https://www.wikidata.org/wiki/Q7119642","display_name":"PLL multibit","level":4,"score":0.4278544783592224},{"id":"https://openalex.org/C119599485","wikidata":"https://www.wikidata.org/wiki/Q43035","display_name":"Electrical engineering","level":1,"score":0.4078006148338318},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.3748597502708435},{"id":"https://openalex.org/C165801399","wikidata":"https://www.wikidata.org/wiki/Q25428","display_name":"Voltage","level":2,"score":0.3573257029056549},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.28395378589630127},{"id":"https://openalex.org/C114614502","wikidata":"https://www.wikidata.org/wiki/Q76592","display_name":"Combinatorics","level":1,"score":0.0},{"id":"https://openalex.org/C33923547","wikidata":"https://www.wikidata.org/wiki/Q395","display_name":"Mathematics","level":0,"score":0.0},{"id":"https://openalex.org/C199360897","wikidata":"https://www.wikidata.org/wiki/Q9143","display_name":"Programming language","level":1,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/icecs.2007.4510922","is_oa":false,"landing_page_url":"https://doi.org/10.1109/icecs.2007.4510922","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2007 14th IEEE International Conference on Electronics, Circuits and Systems","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[{"display_name":"Affordable and clean energy","score":0.8700000047683716,"id":"https://metadata.un.org/sdg/7"}],"awards":[],"funders":[],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":7,"referenced_works":["https://openalex.org/W1599598775","https://openalex.org/W2062327827","https://openalex.org/W2104340505","https://openalex.org/W2110144707","https://openalex.org/W2119955099","https://openalex.org/W2148568726","https://openalex.org/W2169411838"],"related_works":["https://openalex.org/W2141726610","https://openalex.org/W2061664740","https://openalex.org/W2540766993","https://openalex.org/W4242529045","https://openalex.org/W2911266525","https://openalex.org/W2086169776","https://openalex.org/W2017334866","https://openalex.org/W2100673396","https://openalex.org/W2976219355","https://openalex.org/W786718093"],"abstract_inverted_index":{"The":[0,24,56],"feasibility":[1],"of":[2,37,47],"low":[3],"noise":[4,36],"sensitivity":[5],"2.4-GHz":[6],"Phase":[7],"Locked":[8],"Loop":[9],"for":[10],"use":[11],"in":[12,18],"wireless":[13],"communications":[14],"as":[15,17],"well":[16],"clock":[19],"generation":[20],"circuit":[21],"is":[22],"demonstrated.":[23],"system":[25],"uses":[26],"low-":[27],"gain-multi-band":[28],"Voltage":[29],"Controlled":[30],"Oscillator":[31],"which":[32],"achieves":[33],"a":[34,44],"phase":[35],"-98":[38],"dBc/Hz":[39],"@":[40],"1MHz":[41],"offset":[42],"while":[43],"lock":[45],"time":[46],"150-\u03bcs":[48],"has":[49,58],"been":[50,59],"obtained":[51],"from":[52],"the":[53],"PLL":[54],"loop.":[55],"design":[57],"implemented":[60],"on":[61],"standard":[62],"CMOS":[63],"technology.":[64]},"counts_by_year":[{"year":2022,"cited_by_count":1},{"year":2017,"cited_by_count":1},{"year":2016,"cited_by_count":1},{"year":2014,"cited_by_count":2},{"year":2012,"cited_by_count":1}],"updated_date":"2026-03-20T20:47:17.329874","created_date":"2025-10-10T00:00:00"}