{"id":"https://openalex.org/W4392248616","doi":"https://doi.org/10.1109/icce59016.2024.10444470","title":"A Productive HLS Simulation Approach for Multi-FPGA Systems","display_name":"A Productive HLS Simulation Approach for Multi-FPGA Systems","publication_year":2024,"publication_date":"2024-01-06","ids":{"openalex":"https://openalex.org/W4392248616","doi":"https://doi.org/10.1109/icce59016.2024.10444470"},"language":"en","primary_location":{"id":"doi:10.1109/icce59016.2024.10444470","is_oa":false,"landing_page_url":"http://dx.doi.org/10.1109/icce59016.2024.10444470","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2024 IEEE International Conference on Consumer Electronics (ICCE)","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5024093446","display_name":"Haruto Ikehara","orcid":null},"institutions":[{"id":"https://openalex.org/I43777268","display_name":"Nagasaki University","ror":"https://ror.org/058h74p94","country_code":"JP","type":"education","lineage":["https://openalex.org/I43777268"]}],"countries":["JP"],"is_corresponding":true,"raw_author_name":"Haruto Ikehara","raw_affiliation_strings":["Nagasaki University, 1&#x2013;14 Bunkyo-machi, Nagasaki-shi,Graduate School of Engineering,Nagasaki"],"affiliations":[{"raw_affiliation_string":"Nagasaki University, 1&#x2013;14 Bunkyo-machi, Nagasaki-shi,Graduate School of Engineering,Nagasaki","institution_ids":["https://openalex.org/I43777268"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5108249863","display_name":"Taito Manabe","orcid":null},"institutions":[{"id":"https://openalex.org/I43777268","display_name":"Nagasaki University","ror":"https://ror.org/058h74p94","country_code":"JP","type":"education","lineage":["https://openalex.org/I43777268"]}],"countries":["JP"],"is_corresponding":false,"raw_author_name":"Taito Manabe","raw_affiliation_strings":["Nagasaki University, 1&#x2013;14 Bunkyo-machi, Nagasaki-shi,Graduate School of Engineering,Nagasaki"],"affiliations":[{"raw_affiliation_string":"Nagasaki University, 1&#x2013;14 Bunkyo-machi, Nagasaki-shi,Graduate School of Engineering,Nagasaki","institution_ids":["https://openalex.org/I43777268"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5106183057","display_name":"Yuichiro Shibata","orcid":null},"institutions":[{"id":"https://openalex.org/I43777268","display_name":"Nagasaki University","ror":"https://ror.org/058h74p94","country_code":"JP","type":"education","lineage":["https://openalex.org/I43777268"]}],"countries":["JP"],"is_corresponding":false,"raw_author_name":"Yuichiro Shibata","raw_affiliation_strings":["Nagasaki University, 1&#x2013;14 Bunkyo-machi, Nagasaki-shi,Graduate School of Engineering,Nagasaki"],"affiliations":[{"raw_affiliation_string":"Nagasaki University, 1&#x2013;14 Bunkyo-machi, Nagasaki-shi,Graduate School of Engineering,Nagasaki","institution_ids":["https://openalex.org/I43777268"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5094023348","display_name":"Tomohiro Uenoy","orcid":null},"institutions":[{"id":"https://openalex.org/I4210129730","display_name":"RIKEN Center for Computational Science","ror":"https://ror.org/03r519674","country_code":"JP","type":"facility","lineage":["https://openalex.org/I4210110652","https://openalex.org/I4210129730"]}],"countries":["JP"],"is_corresponding":false,"raw_author_name":"Tomohiro Uenoy","raw_affiliation_strings":["Riken Center for Computational Science, 7&#x2013;1&#x2013;26 Minatojimaminami-machi, Chuo-ku, Kobe-shi,Hyogo"],"affiliations":[{"raw_affiliation_string":"Riken Center for Computational Science, 7&#x2013;1&#x2013;26 Minatojimaminami-machi, Chuo-ku, Kobe-shi,Hyogo","institution_ids":["https://openalex.org/I4210129730"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5094023349","display_name":"Kentaro Sanoy","orcid":null},"institutions":[{"id":"https://openalex.org/I4210129730","display_name":"RIKEN Center for Computational Science","ror":"https://ror.org/03r519674","country_code":"JP","type":"facility","lineage":["https://openalex.org/I4210110652","https://openalex.org/I4210129730"]}],"countries":["JP"],"is_corresponding":false,"raw_author_name":"Kentaro Sanoy","raw_affiliation_strings":["Riken Center for Computational Science, 7&#x2013;1&#x2013;26 Minatojimaminami-machi, Chuo-ku, Kobe-shi,Hyogo"],"affiliations":[{"raw_affiliation_string":"Riken Center for Computational Science, 7&#x2013;1&#x2013;26 Minatojimaminami-machi, Chuo-ku, Kobe-shi,Hyogo","institution_ids":["https://openalex.org/I4210129730"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":5,"corresponding_author_ids":["https://openalex.org/A5024093446"],"corresponding_institution_ids":["https://openalex.org/I43777268"],"apc_list":null,"apc_paid":null,"fwci":0.0,"has_fulltext":false,"cited_by_count":0,"citation_normalized_percentile":{"value":0.01634112,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":null,"biblio":{"volume":"30","issue":null,"first_page":"1","last_page":"2"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10904","display_name":"Embedded Systems Design Techniques","score":0.9998000264167786,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10904","display_name":"Embedded Systems Design Techniques","score":0.9998000264167786,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11522","display_name":"VLSI and FPGA Design Techniques","score":0.9993000030517578,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11032","display_name":"VLSI and Analog Circuit Testing","score":0.9987999796867371,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.7461828589439392},{"id":"https://openalex.org/keywords/field-programmable-gate-array","display_name":"Field-programmable gate array","score":0.7404839992523193},{"id":"https://openalex.org/keywords/computer-architecture","display_name":"Computer architecture","score":0.5167369246482849},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.47466257214546204},{"id":"https://openalex.org/keywords/high-level-synthesis","display_name":"High-level synthesis","score":0.43115025758743286},{"id":"https://openalex.org/keywords/parallel-computing","display_name":"Parallel computing","score":0.359630286693573}],"concepts":[{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.7461828589439392},{"id":"https://openalex.org/C42935608","wikidata":"https://www.wikidata.org/wiki/Q190411","display_name":"Field-programmable gate array","level":2,"score":0.7404839992523193},{"id":"https://openalex.org/C118524514","wikidata":"https://www.wikidata.org/wiki/Q173212","display_name":"Computer architecture","level":1,"score":0.5167369246482849},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.47466257214546204},{"id":"https://openalex.org/C58013763","wikidata":"https://www.wikidata.org/wiki/Q5754574","display_name":"High-level synthesis","level":3,"score":0.43115025758743286},{"id":"https://openalex.org/C173608175","wikidata":"https://www.wikidata.org/wiki/Q232661","display_name":"Parallel computing","level":1,"score":0.359630286693573}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/icce59016.2024.10444470","is_oa":false,"landing_page_url":"http://dx.doi.org/10.1109/icce59016.2024.10444470","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2024 IEEE International Conference on Consumer Electronics (ICCE)","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[{"id":"https://metadata.un.org/sdg/8","display_name":"Decent work and economic growth","score":0.5099999904632568}],"awards":[],"funders":[],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":4,"referenced_works":["https://openalex.org/W2343695530","https://openalex.org/W2894759027","https://openalex.org/W2942646047","https://openalex.org/W4316658604"],"related_works":["https://openalex.org/W2096844293","https://openalex.org/W2363944576","https://openalex.org/W2612099726","https://openalex.org/W2351041855","https://openalex.org/W2570254841","https://openalex.org/W1967938402","https://openalex.org/W2386041993","https://openalex.org/W2160632767","https://openalex.org/W1608572506","https://openalex.org/W2135482679"],"abstract_inverted_index":{"When":[0],"implementing":[1],"an":[2,5],"application":[3],"on":[4],"FPGA":[6],"cluster":[7],"with":[8,21],"multiple":[9,46,66],"FPGAs":[10,67],"connected,":[11],"the":[12,34,56],"existing":[13],"high-level":[14],"synthesis":[15],"design":[16],"environment":[17],"assumes":[18],"functional":[19],"simulation":[20],"a":[22,28,51,71,74],"single":[23],"module,":[24],"and":[25],"it":[26],"requires":[27],"great":[29],"deal":[30],"of":[31,58,65],"effort":[32],"by":[33,61],"designer":[35],"to":[36,53],"create":[37],"verification":[38],"code":[39],"for":[40],"processes":[41],"that":[42],"reproduce":[43],"communication":[44],"among":[45],"modules.":[47],"Therefore,":[48],"we":[49],"propose":[50],"method":[52],"easily":[54],"simulate":[55],"function":[57],"multi-FPGA":[59],"systems":[60],"executing":[62],"each":[63],"process":[64],"in":[68],"parallel":[69],"as":[70],"task":[72],"through":[73],"system-of-tasks":[75],"feature.":[76]},"counts_by_year":[],"updated_date":"2025-12-21T01:58:51.020947","created_date":"2025-10-10T00:00:00"}
