{"id":"https://openalex.org/W2554943244","doi":"https://doi.org/10.1109/iccd.2016.7753333","title":"A 64 kb differential single-port 12T SRAM design with a bit-interleaving scheme for low-voltage operation in 32 nm SOI CMOS","display_name":"A 64 kb differential single-port 12T SRAM design with a bit-interleaving scheme for low-voltage operation in 32 nm SOI CMOS","publication_year":2016,"publication_date":"2016-10-01","ids":{"openalex":"https://openalex.org/W2554943244","doi":"https://doi.org/10.1109/iccd.2016.7753333","mag":"2554943244"},"language":"en","primary_location":{"id":"doi:10.1109/iccd.2016.7753333","is_oa":false,"landing_page_url":"https://doi.org/10.1109/iccd.2016.7753333","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2016 IEEE 34th International Conference on Computer Design (ICCD)","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":true,"oa_status":"green","oa_url":"https://escholarship.org/content/qt99f6q9c9/qt99f6q9c9.pdf?t=oo8qk6","any_repository_has_fulltext":true},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5013842248","display_name":"Samira Ataei","orcid":null},"institutions":[{"id":"https://openalex.org/I115475287","display_name":"Oklahoma State University","ror":"https://ror.org/01g9vbr38","country_code":"US","type":"education","lineage":["https://openalex.org/I115475287"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Samira Ataei","raw_affiliation_strings":["Electrical and Computer Engineering Department, Oklahoma State University, Stillwater, OK"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Electrical and Computer Engineering Department, Oklahoma State University, Stillwater, OK","institution_ids":["https://openalex.org/I115475287"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5033770307","display_name":"James E. Stine","orcid":"https://orcid.org/0000-0001-8767-390X"},"institutions":[{"id":"https://openalex.org/I115475287","display_name":"Oklahoma State University","ror":"https://ror.org/01g9vbr38","country_code":"US","type":"education","lineage":["https://openalex.org/I115475287"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"James E. Stine","raw_affiliation_strings":["Electrical and Computer Engineering Department, Oklahoma State University, Stillwater, OK"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Electrical and Computer Engineering Department, Oklahoma State University, Stillwater, OK","institution_ids":["https://openalex.org/I115475287"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5065218759","display_name":"Matthew R. Guthaus","orcid":"https://orcid.org/0000-0002-8113-4531"},"institutions":[{"id":"https://openalex.org/I185103710","display_name":"University of California, Santa Cruz","ror":"https://ror.org/03s65by71","country_code":"US","type":"education","lineage":["https://openalex.org/I185103710"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Matthew R. Guthaus","raw_affiliation_strings":["Department of Computer Engineering, University of California Santa Cruz, Santa Cruz, CA"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Department of Computer Engineering, University of California Santa Cruz, Santa Cruz, CA","institution_ids":["https://openalex.org/I185103710"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":3,"corresponding_author_ids":[],"corresponding_institution_ids":[],"apc_list":null,"apc_paid":null,"fwci":1.3021,"has_fulltext":true,"cited_by_count":18,"citation_normalized_percentile":{"value":0.83102372,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":90,"max":98},"biblio":{"volume":null,"issue":null,"first_page":"499","last_page":"506"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10472","display_name":"Semiconductor materials and devices","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10558","display_name":"Advancements in Semiconductor Devices and Circuit Design","score":0.9998000264167786,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/static-random-access-memory","display_name":"Static random-access memory","score":0.7505559921264648},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.6701644659042358},{"id":"https://openalex.org/keywords/cmos","display_name":"CMOS","score":0.6216970086097717},{"id":"https://openalex.org/keywords/interleaving","display_name":"Interleaving","score":0.5415146946907043},{"id":"https://openalex.org/keywords/sense-amplifier","display_name":"Sense amplifier","score":0.5000321865081787},{"id":"https://openalex.org/keywords/electronic-engineering","display_name":"Electronic engineering","score":0.49363863468170166},{"id":"https://openalex.org/keywords/computer-hardware","display_name":"Computer hardware","score":0.47287485003471375},{"id":"https://openalex.org/keywords/voltage","display_name":"Voltage","score":0.4473435878753662},{"id":"https://openalex.org/keywords/electrical-engineering","display_name":"Electrical engineering","score":0.30978888273239136},{"id":"https://openalex.org/keywords/semiconductor-memory","display_name":"Semiconductor memory","score":0.22410953044891357},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.21853697299957275}],"concepts":[{"id":"https://openalex.org/C68043766","wikidata":"https://www.wikidata.org/wiki/Q267416","display_name":"Static random-access memory","level":2,"score":0.7505559921264648},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.6701644659042358},{"id":"https://openalex.org/C46362747","wikidata":"https://www.wikidata.org/wiki/Q173431","display_name":"CMOS","level":2,"score":0.6216970086097717},{"id":"https://openalex.org/C28034677","wikidata":"https://www.wikidata.org/wiki/Q17092530","display_name":"Interleaving","level":2,"score":0.5415146946907043},{"id":"https://openalex.org/C32666082","wikidata":"https://www.wikidata.org/wiki/Q7450979","display_name":"Sense amplifier","level":3,"score":0.5000321865081787},{"id":"https://openalex.org/C24326235","wikidata":"https://www.wikidata.org/wiki/Q126095","display_name":"Electronic engineering","level":1,"score":0.49363863468170166},{"id":"https://openalex.org/C9390403","wikidata":"https://www.wikidata.org/wiki/Q3966","display_name":"Computer hardware","level":1,"score":0.47287485003471375},{"id":"https://openalex.org/C165801399","wikidata":"https://www.wikidata.org/wiki/Q25428","display_name":"Voltage","level":2,"score":0.4473435878753662},{"id":"https://openalex.org/C119599485","wikidata":"https://www.wikidata.org/wiki/Q43035","display_name":"Electrical engineering","level":1,"score":0.30978888273239136},{"id":"https://openalex.org/C98986596","wikidata":"https://www.wikidata.org/wiki/Q1143031","display_name":"Semiconductor memory","level":2,"score":0.22410953044891357},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.21853697299957275}],"mesh":[],"locations_count":3,"locations":[{"id":"doi:10.1109/iccd.2016.7753333","is_oa":false,"landing_page_url":"https://doi.org/10.1109/iccd.2016.7753333","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2016 IEEE 34th International Conference on Computer Design (ICCD)","raw_type":"proceedings-article"},{"id":"pmh:oai:escholarship.org:ark:/13030/qt99f6q9c9","is_oa":true,"landing_page_url":"https://escholarship.org/uc/item/99f6q9c9","pdf_url":"https://escholarship.org/content/qt99f6q9c9/qt99f6q9c9.pdf?t=oo8qk6","source":{"id":"https://openalex.org/S4306400115","display_name":"eScholarship (California Digital Library)","issn_l":null,"issn":null,"is_oa":false,"is_in_doaj":false,"is_core":false,"host_organization":"https://openalex.org/I2801248553","host_organization_name":"California Digital Library","host_organization_lineage":["https://openalex.org/I2801248553"],"host_organization_lineage_names":[],"type":"repository"},"license":null,"license_id":null,"version":"submittedVersion","is_accepted":false,"is_published":false,"raw_source_name":"","raw_type":"article"},{"id":"pmh:qt99f6q9c9","is_oa":false,"landing_page_url":"http://www.escholarship.org/uc/item/99f6q9c9","pdf_url":null,"source":{"id":"https://openalex.org/S4306400115","display_name":"eScholarship (California Digital Library)","issn_l":null,"issn":null,"is_oa":false,"is_in_doaj":false,"is_core":false,"host_organization":"https://openalex.org/I2801248553","host_organization_name":"California Digital Library","host_organization_lineage":["https://openalex.org/I2801248553"],"host_organization_lineage_names":[],"type":"repository"},"license":null,"license_id":null,"version":"submittedVersion","is_accepted":false,"is_published":false,"raw_source_name":"Ataei, S; Stine, JE; Guthaus, MR; & IEEE,. (2016). A 64 kb Differential Single-Port 12T SRAM Design With a Bit-Interleaving Scheme for Low-Voltage Operation in 32 nm SOI CMOS. PROCEEDINGS OF THE 34TH IEEE INTERNATIONAL CONFERENCE ON COMPUTER DESIGN (ICCD), 499 - 506. UC Santa Cruz: Retrieved from: http://www.escholarship.org/uc/item/99f6q9c9","raw_type":"article"}],"best_oa_location":{"id":"pmh:oai:escholarship.org:ark:/13030/qt99f6q9c9","is_oa":true,"landing_page_url":"https://escholarship.org/uc/item/99f6q9c9","pdf_url":"https://escholarship.org/content/qt99f6q9c9/qt99f6q9c9.pdf?t=oo8qk6","source":{"id":"https://openalex.org/S4306400115","display_name":"eScholarship (California Digital Library)","issn_l":null,"issn":null,"is_oa":false,"is_in_doaj":false,"is_core":false,"host_organization":"https://openalex.org/I2801248553","host_organization_name":"California Digital Library","host_organization_lineage":["https://openalex.org/I2801248553"],"host_organization_lineage_names":[],"type":"repository"},"license":null,"license_id":null,"version":"submittedVersion","is_accepted":false,"is_published":false,"raw_source_name":"","raw_type":"article"},"sustainable_development_goals":[{"score":0.8100000023841858,"display_name":"Affordable and clean energy","id":"https://metadata.un.org/sdg/7"}],"awards":[],"funders":[{"id":"https://openalex.org/F4320306076","display_name":"National Science Foundation","ror":"https://ror.org/021nxhr62"}],"has_content":{"grobid_xml":true,"pdf":true},"content_urls":{"pdf":"https://content.openalex.org/works/W2554943244.pdf","grobid_xml":"https://content.openalex.org/works/W2554943244.grobid-xml"},"referenced_works_count":24,"referenced_works":["https://openalex.org/W1518236483","https://openalex.org/W1605313066","https://openalex.org/W1974982221","https://openalex.org/W1978783977","https://openalex.org/W1995329733","https://openalex.org/W2045074698","https://openalex.org/W2047737410","https://openalex.org/W2058679903","https://openalex.org/W2069909337","https://openalex.org/W2099087448","https://openalex.org/W2100483769","https://openalex.org/W2100503779","https://openalex.org/W2105175332","https://openalex.org/W2106339466","https://openalex.org/W2120000030","https://openalex.org/W2127628206","https://openalex.org/W2144289559","https://openalex.org/W2537959404","https://openalex.org/W2579777598","https://openalex.org/W3148792909","https://openalex.org/W4376999389","https://openalex.org/W6636307923","https://openalex.org/W6679781275","https://openalex.org/W6732888495"],"related_works":["https://openalex.org/W1835913819","https://openalex.org/W2548084981","https://openalex.org/W2051363901","https://openalex.org/W2127348582","https://openalex.org/W2136142653","https://openalex.org/W2373152541","https://openalex.org/W2174410816","https://openalex.org/W3209598999","https://openalex.org/W2159817233","https://openalex.org/W2107909712"],"abstract_inverted_index":{"In":[0],"this":[1,44,74],"paper,":[2],"a":[3,15,40,47,52,129,149],"novel":[4],"differential":[5],"single-port":[6],"12T":[7,102,152],"SRAM":[8,153],"bitcell":[9,13,45,75,103],"is":[10,155],"presented.":[11],"This":[12,118],"uses":[14],"read":[16,20,24,28,77,116],"buffer":[17],"to":[18,33,55,92,167],"eliminate":[19],"disturbance,":[21],"improves":[22],"the":[23,68,132],"stability":[25],"and":[26,70,78,113,135,145],"achieves":[27],"static":[29,36],"noise":[30,37],"margin":[31],"equal":[32],"its":[34],"hold":[35],"margin.":[38],"Using":[39,147],"column-based":[41],"select":[42,71],"signal":[43,72],"provides":[46,114,128],"half-select":[48],"free":[49],"feature,":[50],"facilitating":[51],"bit-interleaving":[53],"structure":[54],"reduce":[56],"multi-bit":[57],"soft":[58],"errors":[59],"by":[60],"conventional":[61],"error":[62,82],"correcting":[63],"code":[64],"techniques.":[65],"By":[66],"boosting":[67],"wordline":[69],"voltage,":[73],"can":[76,88],"write":[79],"with":[80,170,181],"no":[81],"at":[83,178],"300":[84],"mV":[85,94],"while":[86,175],"data":[87],"be":[89],"held":[90],"down":[91,166],"250":[93],"in":[95,101,157],"standby":[96],"mode.":[97],"Bitline":[98],"leakage":[99],"suppression":[100],"allows":[104],"more":[105],"bitcells":[106],"per":[107],"bitline":[108],"for":[109,131],"high":[110],"density":[111],"SRAMs":[112],"faster":[115],"operation.":[117],"paper":[119],"also":[120],"introduces":[121],"OpenRAM,":[122,148],"an":[123],"open-source":[124],"memory":[125,139],"compiler,":[126],"that":[127,164],"platform":[130],"generation,":[133],"characterization,":[134],"verification":[136],"of":[137],"fabricable":[138],"designs":[140],"across":[141],"various":[142],"technologies,":[143],"sizes,":[144],"configurations.":[146],"64":[150],"kb":[151],"macro":[154],"designed":[156],"IBM":[158],"32":[159],"nm":[160],"SOI":[161],"CMOS":[162],"technology":[163],"operates":[165],"0.3":[168],"V":[169,180],"50":[171],"MHz":[172],"operating":[173,184],"frequency":[174],"it":[176],"functions":[177],"0.9":[179],"2.2":[182],"GHz":[183],"frequency,":[185],"as":[186],"well.":[187]},"counts_by_year":[{"year":2025,"cited_by_count":2},{"year":2024,"cited_by_count":1},{"year":2023,"cited_by_count":3},{"year":2022,"cited_by_count":1},{"year":2021,"cited_by_count":4},{"year":2019,"cited_by_count":4},{"year":2018,"cited_by_count":1},{"year":2017,"cited_by_count":2}],"updated_date":"2026-06-11T09:08:48.828518","created_date":"2025-10-10T00:00:00"}