{"id":"https://openalex.org/W2123900347","doi":"https://doi.org/10.1109/iccd.2008.4751928","title":"Removing hazards in multi-level logic optimization for generalized fundamental-mode asynchronous circuits","display_name":"Removing hazards in multi-level logic optimization for generalized fundamental-mode asynchronous circuits","publication_year":2008,"publication_date":"2008-10-01","ids":{"openalex":"https://openalex.org/W2123900347","doi":"https://doi.org/10.1109/iccd.2008.4751928","mag":"2123900347"},"language":"en","primary_location":{"id":"doi:10.1109/iccd.2008.4751928","is_oa":false,"landing_page_url":"https://doi.org/10.1109/iccd.2008.4751928","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2008 IEEE International Conference on Computer Design","raw_type":"proceedings-article"},"type":"conference-paper","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5081040738","display_name":"Feng Shi","orcid":"https://orcid.org/0000-0002-3235-9603"},"institutions":[{"id":"https://openalex.org/I53486688","display_name":"Skyworks Solutions (United States)","ror":"https://ror.org/02jymes45","country_code":"US","type":"company","lineage":["https://openalex.org/I53486688"]}],"countries":["US"],"is_corresponding":true,"raw_author_name":"Feng Shi","raw_affiliation_strings":["Skyworks Solutions, Inc., USA",", Skyworks Solutions Inc., Woburn, MA#TAB#"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Skyworks Solutions, Inc., USA","institution_ids":["https://openalex.org/I53486688"]},{"raw_affiliation_string":", Skyworks Solutions Inc., Woburn, MA#TAB#","institution_ids":["https://openalex.org/I53486688"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":1,"corresponding_author_ids":["https://openalex.org/A5081040738"],"corresponding_institution_ids":["https://openalex.org/I53486688"],"apc_list":null,"apc_paid":null,"fwci":null,"has_fulltext":false,"cited_by_count":1,"citation_normalized_percentile":null,"cited_by_percentile_year":null,"biblio":{"volume":null,"issue":null,"first_page":"640","last_page":"645"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11032","display_name":"VLSI and Analog Circuit Testing","score":0.9984999895095825,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11005","display_name":"Radiation Effects in Electronics","score":0.998199999332428,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/hazard","display_name":"Hazard","score":0.7855185270309448},{"id":"https://openalex.org/keywords/asynchronous-communication","display_name":"Asynchronous communication","score":0.7443599104881287},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.7109737396240234},{"id":"https://openalex.org/keywords/asynchronous-circuit","display_name":"Asynchronous circuit","score":0.6308426260948181},{"id":"https://openalex.org/keywords/electronic-circuit","display_name":"Electronic circuit","score":0.5662640333175659},{"id":"https://openalex.org/keywords/logic-synthesis","display_name":"Logic synthesis","score":0.4730329215526581},{"id":"https://openalex.org/keywords/logic-gate","display_name":"Logic gate","score":0.46414509415626526},{"id":"https://openalex.org/keywords/process","display_name":"Process (computing)","score":0.45286980271339417},{"id":"https://openalex.org/keywords/algorithm","display_name":"Algorithm","score":0.42923545837402344},{"id":"https://openalex.org/keywords/synchronous-circuit","display_name":"Synchronous circuit","score":0.26181352138519287},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.16059833765029907},{"id":"https://openalex.org/keywords/electrical-engineering","display_name":"Electrical engineering","score":0.07995635271072388},{"id":"https://openalex.org/keywords/clock-signal","display_name":"Clock signal","score":0.06690642237663269}],"concepts":[{"id":"https://openalex.org/C49261128","wikidata":"https://www.wikidata.org/wiki/Q1132455","display_name":"Hazard","level":2,"score":0.7855185270309448},{"id":"https://openalex.org/C151319957","wikidata":"https://www.wikidata.org/wiki/Q752739","display_name":"Asynchronous communication","level":2,"score":0.7443599104881287},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.7109737396240234},{"id":"https://openalex.org/C87695204","wikidata":"https://www.wikidata.org/wiki/Q629971","display_name":"Asynchronous circuit","level":5,"score":0.6308426260948181},{"id":"https://openalex.org/C134146338","wikidata":"https://www.wikidata.org/wiki/Q1815901","display_name":"Electronic circuit","level":2,"score":0.5662640333175659},{"id":"https://openalex.org/C157922185","wikidata":"https://www.wikidata.org/wiki/Q173198","display_name":"Logic synthesis","level":3,"score":0.4730329215526581},{"id":"https://openalex.org/C131017901","wikidata":"https://www.wikidata.org/wiki/Q170451","display_name":"Logic gate","level":2,"score":0.46414509415626526},{"id":"https://openalex.org/C98045186","wikidata":"https://www.wikidata.org/wiki/Q205663","display_name":"Process (computing)","level":2,"score":0.45286980271339417},{"id":"https://openalex.org/C11413529","wikidata":"https://www.wikidata.org/wiki/Q8366","display_name":"Algorithm","level":1,"score":0.42923545837402344},{"id":"https://openalex.org/C42196554","wikidata":"https://www.wikidata.org/wiki/Q1186179","display_name":"Synchronous circuit","level":4,"score":0.26181352138519287},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.16059833765029907},{"id":"https://openalex.org/C119599485","wikidata":"https://www.wikidata.org/wiki/Q43035","display_name":"Electrical engineering","level":1,"score":0.07995635271072388},{"id":"https://openalex.org/C137059387","wikidata":"https://www.wikidata.org/wiki/Q426882","display_name":"Clock signal","level":3,"score":0.06690642237663269},{"id":"https://openalex.org/C31258907","wikidata":"https://www.wikidata.org/wiki/Q1301371","display_name":"Computer network","level":1,"score":0.0},{"id":"https://openalex.org/C111919701","wikidata":"https://www.wikidata.org/wiki/Q9135","display_name":"Operating system","level":1,"score":0.0},{"id":"https://openalex.org/C178790620","wikidata":"https://www.wikidata.org/wiki/Q11351","display_name":"Organic chemistry","level":1,"score":0.0},{"id":"https://openalex.org/C185592680","wikidata":"https://www.wikidata.org/wiki/Q2329","display_name":"Chemistry","level":0,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/iccd.2008.4751928","is_oa":false,"landing_page_url":"https://doi.org/10.1109/iccd.2008.4751928","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2008 IEEE International Conference on Computer Design","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[],"awards":[],"funders":[],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":21,"referenced_works":["https://openalex.org/W1498870363","https://openalex.org/W1577323490","https://openalex.org/W1665361481","https://openalex.org/W2033724727","https://openalex.org/W2044415289","https://openalex.org/W2095593696","https://openalex.org/W2104949917","https://openalex.org/W2107254242","https://openalex.org/W2108481914","https://openalex.org/W2112835666","https://openalex.org/W2132703725","https://openalex.org/W2143054129","https://openalex.org/W2145480542","https://openalex.org/W2150870594","https://openalex.org/W2167931908","https://openalex.org/W3146410802","https://openalex.org/W4244634726","https://openalex.org/W4285719527","https://openalex.org/W4298011152","https://openalex.org/W6629985922","https://openalex.org/W6676284851"],"related_works":["https://openalex.org/W1948903516","https://openalex.org/W1993985975","https://openalex.org/W2146990170","https://openalex.org/W2187164010","https://openalex.org/W4312516786","https://openalex.org/W2085028021","https://openalex.org/W2138474603","https://openalex.org/W3094139610","https://openalex.org/W937897205","https://openalex.org/W2380707529"],"abstract_inverted_index":{"Unlike":[0],"traditional":[1],"synthesis":[2,29,84],"methods":[3],"for":[4],"fundamental-mode":[5],"asynchronous":[6],"circuits":[7],"which":[8,44],"require":[9],"dedicated":[10],"hazard-free":[11,80],"algorithms,":[12],"a":[13,40,64,79],"multi-level":[14],"logic":[15],"optimization":[16,92],"algorithm":[17,36,85],"is":[18,37,68],"developed":[19],"to":[20,77],"take":[21],"advantage":[22],"of":[23,60],"the":[24,58,61,71,100],"powerful":[25],"and":[26,31,94],"mature":[27],"synchronous":[28,75,91],"algorithms":[30,76,93],"technology":[32,95],"libraries.":[33],"The":[34,82],"proposed":[35,83],"based":[38],"on":[39,70],"hazard":[41,49,65],"analysis":[42],"method,":[43],"not":[45],"only":[46],"detects":[47],"any":[48],"in":[50],"an":[51],"arbitrary":[52],"circuit":[53,72],"structure,":[54],"but":[55],"also":[56],"identifies":[57],"cause":[59],"hazard.":[62],"Then,":[63],"removal":[66],"process":[67],"performed":[69],"synthesized":[73],"using":[74],"generate":[78],"circuit.":[81],"achieves":[86],"high":[87],"efficiency":[88],"by":[89],"exploiting":[90],"libraries,":[96],"as":[97],"demonstrated":[98],"through":[99],"experimental":[101],"results.":[102]},"counts_by_year":[{"year":2012,"cited_by_count":1}],"updated_date":"2026-07-14T23:27:15.235271","created_date":"2025-10-10T00:00:00"}