{"id":"https://openalex.org/W1925663359","doi":"https://doi.org/10.1109/iccd.1994.331947","title":"Initialization issues in the synthesis of asynchronous circuits","display_name":"Initialization issues in the synthesis of asynchronous circuits","publication_year":2002,"publication_date":"2002-12-17","ids":{"openalex":"https://openalex.org/W1925663359","doi":"https://doi.org/10.1109/iccd.1994.331947","mag":"1925663359"},"language":"en","primary_location":{"id":"doi:10.1109/iccd.1994.331947","is_oa":false,"landing_page_url":"https://doi.org/10.1109/iccd.1994.331947","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Proceedings 1994 IEEE International Conference on Computer Design: VLSI in Computers and Processors","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5101911011","display_name":"Serene Banerjee","orcid":"https://orcid.org/0000-0002-5579-4819"},"institutions":[{"id":"https://openalex.org/I24603500","display_name":"University of Massachusetts Amherst","ror":"https://ror.org/0072zz521","country_code":"US","type":"education","lineage":["https://openalex.org/I24603500"]}],"countries":["US"],"is_corresponding":true,"raw_author_name":"S. Banerjee","raw_affiliation_strings":["ECE Department, University of Massachusetts, Amherst, MA, USA"],"affiliations":[{"raw_affiliation_string":"ECE Department, University of Massachusetts, Amherst, MA, USA","institution_ids":["https://openalex.org/I24603500"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5073453545","display_name":"Ranjan Roy","orcid":"https://orcid.org/0000-0003-3072-2162"},"institutions":[],"countries":[],"is_corresponding":false,"raw_author_name":"R.K. Roy","raw_affiliation_strings":["C&C Research Labs, NEC USA, Inc., Princeton, NJ, USA"],"affiliations":[{"raw_affiliation_string":"C&C Research Labs, NEC USA, Inc., Princeton, NJ, USA","institution_ids":[]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5042424184","display_name":"Srimat Chakradhar","orcid":"https://orcid.org/0000-0003-3530-3901"},"institutions":[],"countries":[],"is_corresponding":false,"raw_author_name":"S.T. Chakradhar","raw_affiliation_strings":["C&C Research Labs, NEC USA, Inc., Princeton, NJ, USA"],"affiliations":[{"raw_affiliation_string":"C&C Research Labs, NEC USA, Inc., Princeton, NJ, USA","institution_ids":[]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5113458314","display_name":"Dhiraj K. Pradhan","orcid":null},"institutions":[{"id":"https://openalex.org/I91045830","display_name":"Texas A&M University","ror":"https://ror.org/01f5ytq51","country_code":"US","type":"education","lineage":["https://openalex.org/I91045830"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"D.K. Pradhan","raw_affiliation_strings":["CS Department, Texas A and M University, College Station, TX, USA"],"affiliations":[{"raw_affiliation_string":"CS Department, Texas A and M University, College Station, TX, USA","institution_ids":["https://openalex.org/I91045830"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":4,"corresponding_author_ids":["https://openalex.org/A5101911011"],"corresponding_institution_ids":["https://openalex.org/I24603500"],"apc_list":null,"apc_paid":null,"fwci":1.0183,"has_fulltext":false,"cited_by_count":5,"citation_normalized_percentile":{"value":0.74732639,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":null,"biblio":{"volume":null,"issue":null,"first_page":"447","last_page":"452"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":0.9993000030517578,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":0.9993000030517578,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10142","display_name":"Formal Methods in Verification","score":0.9990000128746033,"subfield":{"id":"https://openalex.org/subfields/1703","display_name":"Computational Theory and Mathematics"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11522","display_name":"VLSI and FPGA Design Techniques","score":0.9984999895095825,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/asynchronous-communication","display_name":"Asynchronous communication","score":0.7876222133636475},{"id":"https://openalex.org/keywords/initialization","display_name":"Initialization","score":0.7453205585479736},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.7282784581184387},{"id":"https://openalex.org/keywords/asynchronous-circuit","display_name":"Asynchronous circuit","score":0.6139700412750244},{"id":"https://openalex.org/keywords/concurrency","display_name":"Concurrency","score":0.5959555506706238},{"id":"https://openalex.org/keywords/electronic-circuit","display_name":"Electronic circuit","score":0.5034210085868835},{"id":"https://openalex.org/keywords/hazard","display_name":"Hazard","score":0.45260918140411377},{"id":"https://openalex.org/keywords/signal","display_name":"SIGNAL (programming language)","score":0.4246181845664978},{"id":"https://openalex.org/keywords/theoretical-computer-science","display_name":"Theoretical computer science","score":0.408569872379303},{"id":"https://openalex.org/keywords/algorithm","display_name":"Algorithm","score":0.39930760860443115},{"id":"https://openalex.org/keywords/programming-language","display_name":"Programming language","score":0.36993616819381714},{"id":"https://openalex.org/keywords/parallel-computing","display_name":"Parallel computing","score":0.3303610682487488},{"id":"https://openalex.org/keywords/clock-signal","display_name":"Clock signal","score":0.1147940456867218},{"id":"https://openalex.org/keywords/telecommunications","display_name":"Telecommunications","score":0.08026659488677979},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.0765785276889801}],"concepts":[{"id":"https://openalex.org/C151319957","wikidata":"https://www.wikidata.org/wiki/Q752739","display_name":"Asynchronous communication","level":2,"score":0.7876222133636475},{"id":"https://openalex.org/C114466953","wikidata":"https://www.wikidata.org/wiki/Q6034165","display_name":"Initialization","level":2,"score":0.7453205585479736},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.7282784581184387},{"id":"https://openalex.org/C87695204","wikidata":"https://www.wikidata.org/wiki/Q629971","display_name":"Asynchronous circuit","level":5,"score":0.6139700412750244},{"id":"https://openalex.org/C193702766","wikidata":"https://www.wikidata.org/wiki/Q1414548","display_name":"Concurrency","level":2,"score":0.5959555506706238},{"id":"https://openalex.org/C134146338","wikidata":"https://www.wikidata.org/wiki/Q1815901","display_name":"Electronic circuit","level":2,"score":0.5034210085868835},{"id":"https://openalex.org/C49261128","wikidata":"https://www.wikidata.org/wiki/Q1132455","display_name":"Hazard","level":2,"score":0.45260918140411377},{"id":"https://openalex.org/C2779843651","wikidata":"https://www.wikidata.org/wiki/Q7390335","display_name":"SIGNAL (programming language)","level":2,"score":0.4246181845664978},{"id":"https://openalex.org/C80444323","wikidata":"https://www.wikidata.org/wiki/Q2878974","display_name":"Theoretical computer science","level":1,"score":0.408569872379303},{"id":"https://openalex.org/C11413529","wikidata":"https://www.wikidata.org/wiki/Q8366","display_name":"Algorithm","level":1,"score":0.39930760860443115},{"id":"https://openalex.org/C199360897","wikidata":"https://www.wikidata.org/wiki/Q9143","display_name":"Programming language","level":1,"score":0.36993616819381714},{"id":"https://openalex.org/C173608175","wikidata":"https://www.wikidata.org/wiki/Q232661","display_name":"Parallel computing","level":1,"score":0.3303610682487488},{"id":"https://openalex.org/C137059387","wikidata":"https://www.wikidata.org/wiki/Q426882","display_name":"Clock signal","level":3,"score":0.1147940456867218},{"id":"https://openalex.org/C76155785","wikidata":"https://www.wikidata.org/wiki/Q418","display_name":"Telecommunications","level":1,"score":0.08026659488677979},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.0765785276889801},{"id":"https://openalex.org/C185592680","wikidata":"https://www.wikidata.org/wiki/Q2329","display_name":"Chemistry","level":0,"score":0.0},{"id":"https://openalex.org/C119599485","wikidata":"https://www.wikidata.org/wiki/Q43035","display_name":"Electrical engineering","level":1,"score":0.0},{"id":"https://openalex.org/C134652429","wikidata":"https://www.wikidata.org/wiki/Q1052698","display_name":"Jitter","level":2,"score":0.0},{"id":"https://openalex.org/C42196554","wikidata":"https://www.wikidata.org/wiki/Q1186179","display_name":"Synchronous circuit","level":4,"score":0.0},{"id":"https://openalex.org/C178790620","wikidata":"https://www.wikidata.org/wiki/Q11351","display_name":"Organic chemistry","level":1,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/iccd.1994.331947","is_oa":false,"landing_page_url":"https://doi.org/10.1109/iccd.1994.331947","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Proceedings 1994 IEEE International Conference on Computer Design: VLSI in Computers and Processors","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[{"score":0.5199999809265137,"display_name":"Peace, Justice and strong institutions","id":"https://metadata.un.org/sdg/16"}],"awards":[],"funders":[],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":7,"referenced_works":["https://openalex.org/W1517543005","https://openalex.org/W1543642100","https://openalex.org/W1554812212","https://openalex.org/W1879281873","https://openalex.org/W2121914493","https://openalex.org/W2535312374","https://openalex.org/W4302458519"],"related_works":["https://openalex.org/W1993985975","https://openalex.org/W1948903516","https://openalex.org/W3094139610","https://openalex.org/W2187164010","https://openalex.org/W4312516786","https://openalex.org/W2138474603","https://openalex.org/W2146990170","https://openalex.org/W937897205","https://openalex.org/W2085028021","https://openalex.org/W2093992207"],"abstract_inverted_index":{"We":[0],"present":[1],"a":[2,26,61,67],"procedure":[3],"for":[4,21,60],"synthesizing":[5],"initializable":[6,37],"asynchronous":[7],"circuits":[8],"from":[9],"functionally":[10,36],"uninitializable":[11],"Signal":[12],"Transition":[13],"Graphs":[14],"(STG).":[15],"After":[16],"characterizing":[17],"the":[18,30,53,57],"necessary":[19],"conditions":[20],"functional":[22],"uninitializability,":[23],"we":[24],"propose":[25],"technique":[27],"that":[28,42],"transforms":[29],"original":[31],"STG":[32,58],"into":[33],"an":[34],"equivalent,":[35],"STG.":[38],"It":[39],"is":[40],"shown":[41],"initializability":[43],"can":[44],"be":[45],"achieved":[46],"by":[47],"sacrificing":[48],"minimal":[49],"concurrency":[50],"without":[51],"violating":[52],"syntactic":[54],"properties":[55],"of":[56,66],"required":[59],"hazard-free":[62],"implementation.":[63],"The":[64],"synthesis":[65],"trigger":[68],"module":[69],"illustrates":[70],"this":[71],"procedure.<":[72],"<ETX":[73],"xmlns:mml=\"http://www.w3.org/1998/Math/MathML\"":[74],"xmlns:xlink=\"http://www.w3.org/1999/xlink\">&gt;</ETX>":[75]},"counts_by_year":[],"updated_date":"2025-11-06T03:46:38.306776","created_date":"2025-10-10T00:00:00"}
