{"id":"https://openalex.org/W2141378131","doi":"https://doi.org/10.1109/iccd.1994.331892","title":"Performance analysis and optimization of asynchronous circuits","display_name":"Performance analysis and optimization of asynchronous circuits","publication_year":2002,"publication_date":"2002-12-17","ids":{"openalex":"https://openalex.org/W2141378131","doi":"https://doi.org/10.1109/iccd.1994.331892","mag":"2141378131"},"language":"en","primary_location":{"id":"doi:10.1109/iccd.1994.331892","is_oa":false,"landing_page_url":"https://doi.org/10.1109/iccd.1994.331892","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Proceedings 1994 IEEE International Conference on Computer Design: VLSI in Computers and Processors","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5080747890","display_name":"Prabhakar Kudva","orcid":"https://orcid.org/0000-0003-0854-8612"},"institutions":[{"id":"https://openalex.org/I223532165","display_name":"University of Utah","ror":"https://ror.org/03r0ha626","country_code":"US","type":"education","lineage":["https://openalex.org/I223532165"]}],"countries":["US"],"is_corresponding":true,"raw_author_name":"P. Kudva","raw_affiliation_strings":["Department of Computer Science, University of Utah, Salt Lake, UT, USA","[Dept. of Comput. Sci., Utah Univ., Salt Lake City, UT, USA]"],"affiliations":[{"raw_affiliation_string":"Department of Computer Science, University of Utah, Salt Lake, UT, USA","institution_ids":["https://openalex.org/I223532165"]},{"raw_affiliation_string":"[Dept. of Comput. Sci., Utah Univ., Salt Lake City, UT, USA]","institution_ids":["https://openalex.org/I223532165"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5069846379","display_name":"Ganesh Gopalakrishnan","orcid":"https://orcid.org/0000-0002-3705-0031"},"institutions":[{"id":"https://openalex.org/I223532165","display_name":"University of Utah","ror":"https://ror.org/03r0ha626","country_code":"US","type":"education","lineage":["https://openalex.org/I223532165"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"G. Gopalakrishnan","raw_affiliation_strings":["Department of Computer Science, University of Utah, Salt Lake, UT, USA","[Dept. of Comput. Sci., Utah Univ., Salt Lake City, UT, USA]"],"affiliations":[{"raw_affiliation_string":"Department of Computer Science, University of Utah, Salt Lake, UT, USA","institution_ids":["https://openalex.org/I223532165"]},{"raw_affiliation_string":"[Dept. of Comput. Sci., Utah Univ., Salt Lake City, UT, USA]","institution_ids":["https://openalex.org/I223532165"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5014880542","display_name":"Erik Brunvand","orcid":"https://orcid.org/0000-0001-8881-927X"},"institutions":[{"id":"https://openalex.org/I223532165","display_name":"University of Utah","ror":"https://ror.org/03r0ha626","country_code":"US","type":"education","lineage":["https://openalex.org/I223532165"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"E. Brunvand","raw_affiliation_strings":["Department of Computer Science, University of Utah, Salt Lake, UT, USA","[Dept. of Comput. Sci., Utah Univ., Salt Lake City, UT, USA]"],"affiliations":[{"raw_affiliation_string":"Department of Computer Science, University of Utah, Salt Lake, UT, USA","institution_ids":["https://openalex.org/I223532165"]},{"raw_affiliation_string":"[Dept. of Comput. Sci., Utah Univ., Salt Lake City, UT, USA]","institution_ids":["https://openalex.org/I223532165"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5089377852","display_name":"Venkatesh Akella","orcid":"https://orcid.org/0000-0003-3014-5326"},"institutions":[{"id":"https://openalex.org/I223532165","display_name":"University of Utah","ror":"https://ror.org/03r0ha626","country_code":"US","type":"education","lineage":["https://openalex.org/I223532165"]},{"id":"https://openalex.org/I84218800","display_name":"University of California, Davis","ror":"https://ror.org/05rrcem69","country_code":"US","type":"education","lineage":["https://openalex.org/I84218800"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"V. Akella","raw_affiliation_strings":["Department of ECE, University of California, Davis, CA, USA","University of Utah,"],"affiliations":[{"raw_affiliation_string":"Department of ECE, University of California, Davis, CA, USA","institution_ids":["https://openalex.org/I84218800"]},{"raw_affiliation_string":"University of Utah,","institution_ids":["https://openalex.org/I223532165"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":4,"corresponding_author_ids":["https://openalex.org/A5080747890"],"corresponding_institution_ids":["https://openalex.org/I223532165"],"apc_list":null,"apc_paid":null,"fwci":3.486,"has_fulltext":false,"cited_by_count":37,"citation_normalized_percentile":{"value":0.93463711,"is_in_top_1_percent":false,"is_in_top_10_percent":true},"cited_by_percentile_year":{"min":89,"max":96},"biblio":{"volume":null,"issue":null,"first_page":"221","last_page":"224"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T11125","display_name":"Petri Nets in System Modeling","score":0.9998000264167786,"subfield":{"id":"https://openalex.org/subfields/1703","display_name":"Computational Theory and Mathematics"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T11125","display_name":"Petri Nets in System Modeling","score":0.9998000264167786,"subfield":{"id":"https://openalex.org/subfields/1703","display_name":"Computational Theory and Mathematics"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10142","display_name":"Formal Methods in Verification","score":0.9994000196456909,"subfield":{"id":"https://openalex.org/subfields/1703","display_name":"Computational Theory and Mathematics"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":0.9983000159263611,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/asynchronous-communication","display_name":"Asynchronous communication","score":0.8588030338287354},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.7934972047805786},{"id":"https://openalex.org/keywords/petri-net","display_name":"Petri net","score":0.6795447468757629},{"id":"https://openalex.org/keywords/soundness","display_name":"Soundness","score":0.6791074275970459},{"id":"https://openalex.org/keywords/electronic-circuit","display_name":"Electronic circuit","score":0.6319707632064819},{"id":"https://openalex.org/keywords/very-large-scale-integration","display_name":"Very-large-scale integration","score":0.5004534721374512},{"id":"https://openalex.org/keywords/asynchronous-circuit","display_name":"Asynchronous circuit","score":0.4929389953613281},{"id":"https://openalex.org/keywords/computer-architecture","display_name":"Computer architecture","score":0.4107828140258789},{"id":"https://openalex.org/keywords/computer-engineering","display_name":"Computer engineering","score":0.3968234956264496},{"id":"https://openalex.org/keywords/theoretical-computer-science","display_name":"Theoretical computer science","score":0.35102489590644836},{"id":"https://openalex.org/keywords/algorithm","display_name":"Algorithm","score":0.2707187235355377},{"id":"https://openalex.org/keywords/programming-language","display_name":"Programming language","score":0.23417210578918457},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.187745600938797},{"id":"https://openalex.org/keywords/jitter","display_name":"Jitter","score":0.1670597493648529},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.09415256977081299},{"id":"https://openalex.org/keywords/telecommunications","display_name":"Telecommunications","score":0.07911506295204163},{"id":"https://openalex.org/keywords/electrical-engineering","display_name":"Electrical engineering","score":0.06732878088951111}],"concepts":[{"id":"https://openalex.org/C151319957","wikidata":"https://www.wikidata.org/wiki/Q752739","display_name":"Asynchronous communication","level":2,"score":0.8588030338287354},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.7934972047805786},{"id":"https://openalex.org/C38677869","wikidata":"https://www.wikidata.org/wiki/Q724168","display_name":"Petri net","level":2,"score":0.6795447468757629},{"id":"https://openalex.org/C39920170","wikidata":"https://www.wikidata.org/wiki/Q693083","display_name":"Soundness","level":2,"score":0.6791074275970459},{"id":"https://openalex.org/C134146338","wikidata":"https://www.wikidata.org/wiki/Q1815901","display_name":"Electronic circuit","level":2,"score":0.6319707632064819},{"id":"https://openalex.org/C14580979","wikidata":"https://www.wikidata.org/wiki/Q876049","display_name":"Very-large-scale integration","level":2,"score":0.5004534721374512},{"id":"https://openalex.org/C87695204","wikidata":"https://www.wikidata.org/wiki/Q629971","display_name":"Asynchronous circuit","level":5,"score":0.4929389953613281},{"id":"https://openalex.org/C118524514","wikidata":"https://www.wikidata.org/wiki/Q173212","display_name":"Computer architecture","level":1,"score":0.4107828140258789},{"id":"https://openalex.org/C113775141","wikidata":"https://www.wikidata.org/wiki/Q428691","display_name":"Computer engineering","level":1,"score":0.3968234956264496},{"id":"https://openalex.org/C80444323","wikidata":"https://www.wikidata.org/wiki/Q2878974","display_name":"Theoretical computer science","level":1,"score":0.35102489590644836},{"id":"https://openalex.org/C11413529","wikidata":"https://www.wikidata.org/wiki/Q8366","display_name":"Algorithm","level":1,"score":0.2707187235355377},{"id":"https://openalex.org/C199360897","wikidata":"https://www.wikidata.org/wiki/Q9143","display_name":"Programming language","level":1,"score":0.23417210578918457},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.187745600938797},{"id":"https://openalex.org/C134652429","wikidata":"https://www.wikidata.org/wiki/Q1052698","display_name":"Jitter","level":2,"score":0.1670597493648529},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.09415256977081299},{"id":"https://openalex.org/C76155785","wikidata":"https://www.wikidata.org/wiki/Q418","display_name":"Telecommunications","level":1,"score":0.07911506295204163},{"id":"https://openalex.org/C119599485","wikidata":"https://www.wikidata.org/wiki/Q43035","display_name":"Electrical engineering","level":1,"score":0.06732878088951111},{"id":"https://openalex.org/C42196554","wikidata":"https://www.wikidata.org/wiki/Q1186179","display_name":"Synchronous circuit","level":4,"score":0.0},{"id":"https://openalex.org/C137059387","wikidata":"https://www.wikidata.org/wiki/Q426882","display_name":"Clock signal","level":3,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/iccd.1994.331892","is_oa":false,"landing_page_url":"https://doi.org/10.1109/iccd.1994.331892","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Proceedings 1994 IEEE International Conference on Computer Design: VLSI in Computers and Processors","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[],"awards":[],"funders":[],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":22,"referenced_works":["https://openalex.org/W1504147341","https://openalex.org/W1536557058","https://openalex.org/W1666015432","https://openalex.org/W1769860851","https://openalex.org/W1967575124","https://openalex.org/W1976287594","https://openalex.org/W1990059550","https://openalex.org/W1992481212","https://openalex.org/W1996109622","https://openalex.org/W2017349948","https://openalex.org/W2050890381","https://openalex.org/W2055284127","https://openalex.org/W2102718251","https://openalex.org/W2125739093","https://openalex.org/W2132385281","https://openalex.org/W2141378131","https://openalex.org/W2151786168","https://openalex.org/W2159261801","https://openalex.org/W2166853570","https://openalex.org/W3147996545","https://openalex.org/W4231905827","https://openalex.org/W6638107592"],"related_works":["https://openalex.org/W1511249877","https://openalex.org/W1578828174","https://openalex.org/W2950376466","https://openalex.org/W2000943029","https://openalex.org/W2621980927","https://openalex.org/W2002878601","https://openalex.org/W4302559785","https://openalex.org/W4312379357","https://openalex.org/W2553925117","https://openalex.org/W2039987950"],"abstract_inverted_index":{"Asynchronous/self-timed":[0],"circuits":[1,47,52],"are":[2,27,64],"beginning":[3],"to":[4,53,66],"attract":[5],"renewed":[6],"attention":[7],"as":[8],"a":[9],"promising":[10],"means":[11],"of":[12,17,37,71,82],"dealing":[13],"with":[14,55,60],"the":[15,35,61,68,80,83],"complexity":[16],"modern":[18],"VLSI":[19],"designs.":[20],"Very":[21],"few":[22],"analysis":[23],"techniques":[24],"or":[25],"tools":[26],"available":[28],"for":[29,42],"estimating":[30],"their":[31],"performance.":[32],"We":[33],"adapt":[34],"theory":[36],"generalized":[38],"timed":[39],"Petri-nets":[40],"(GTPN)":[41],"analyzing":[43],"and":[44],"comparing":[45],"asynchronous":[46,73],"ranging":[48],"from":[49],"purely":[50],"control-oriented":[51],"those":[54],"data":[56],"dependent":[57],"control.":[58],"Experiments":[59],"GTPN":[62],"analyzer":[63],"found":[65],"track":[67],"observed":[69],"performance":[70],"actual":[72],"circuits,":[74],"thereby":[75],"offering":[76],"empirical":[77],"evidence":[78],"towards":[79],"soundness":[81],"modeling":[84],"approach.<":[85],"<ETX":[86],"xmlns:mml=\"http://www.w3.org/1998/Math/MathML\"":[87],"xmlns:xlink=\"http://www.w3.org/1999/xlink\">&gt;</ETX>":[88]},"counts_by_year":[{"year":2023,"cited_by_count":1},{"year":2021,"cited_by_count":1},{"year":2018,"cited_by_count":1},{"year":2015,"cited_by_count":1},{"year":2013,"cited_by_count":2},{"year":2012,"cited_by_count":1}],"updated_date":"2026-03-09T08:58:05.943551","created_date":"2025-10-10T00:00:00"}