{"id":"https://openalex.org/W2152775409","doi":"https://doi.org/10.1109/iccd.1991.139865","title":"Implementation-independent model of an instruction set architecture using VHDL","display_name":"Implementation-independent model of an instruction set architecture using VHDL","publication_year":2002,"publication_date":"2002-12-10","ids":{"openalex":"https://openalex.org/W2152775409","doi":"https://doi.org/10.1109/iccd.1991.139865","mag":"2152775409"},"language":"en","primary_location":{"id":"doi:10.1109/iccd.1991.139865","is_oa":false,"landing_page_url":"https://doi.org/10.1109/iccd.1991.139865","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"[1991 Proceedings] IEEE International Conference on Computer Design: VLSI in Computers and Processors","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5042939580","display_name":"M.H. Salinas","orcid":"https://orcid.org/0000-0002-9408-9418"},"institutions":[{"id":"https://openalex.org/I51556381","display_name":"University of Virginia","ror":"https://ror.org/0153tk833","country_code":"US","type":"education","lineage":["https://openalex.org/I51556381"]}],"countries":["US"],"is_corresponding":true,"raw_author_name":"M.H. Salinas","raw_affiliation_strings":["Center for Semicustom Integrated Systems Department of Electrical Engineering, University of Virginia, Charlottesville, VA, USA"],"affiliations":[{"raw_affiliation_string":"Center for Semicustom Integrated Systems Department of Electrical Engineering, University of Virginia, Charlottesville, VA, USA","institution_ids":["https://openalex.org/I51556381"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5047081697","display_name":"B.W. Johnson","orcid":"https://orcid.org/0000-0003-2849-2126"},"institutions":[{"id":"https://openalex.org/I51556381","display_name":"University of Virginia","ror":"https://ror.org/0153tk833","country_code":"US","type":"education","lineage":["https://openalex.org/I51556381"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"B.W. Johnson","raw_affiliation_strings":["Center for Semicustom Integrated Systems Department of Electrical Engineering, University of Virginia, Charlottesville, VA, USA"],"affiliations":[{"raw_affiliation_string":"Center for Semicustom Integrated Systems Department of Electrical Engineering, University of Virginia, Charlottesville, VA, USA","institution_ids":["https://openalex.org/I51556381"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5044171543","display_name":"J.H. Aylor","orcid":null},"institutions":[{"id":"https://openalex.org/I51556381","display_name":"University of Virginia","ror":"https://ror.org/0153tk833","country_code":"US","type":"education","lineage":["https://openalex.org/I51556381"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"J.H. Aylor","raw_affiliation_strings":["Center for Semicustom Integrated Systems Department of Electrical Engineering, University of Virginia, Charlottesville, VA, USA"],"affiliations":[{"raw_affiliation_string":"Center for Semicustom Integrated Systems Department of Electrical Engineering, University of Virginia, Charlottesville, VA, USA","institution_ids":["https://openalex.org/I51556381"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":3,"corresponding_author_ids":["https://openalex.org/A5042939580"],"corresponding_institution_ids":["https://openalex.org/I51556381"],"apc_list":null,"apc_paid":null,"fwci":0.0,"has_fulltext":false,"cited_by_count":1,"citation_normalized_percentile":{"value":0.21209152,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":null,"biblio":{"volume":null,"issue":null,"first_page":"140","last_page":"145"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10904","display_name":"Embedded Systems Design Techniques","score":0.9994000196456909,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10904","display_name":"Embedded Systems Design Techniques","score":0.9994000196456909,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10054","display_name":"Parallel Computing and Optimization Techniques","score":0.9979000091552734,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10933","display_name":"Real-Time Systems Scheduling","score":0.9936000108718872,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/vhdl","display_name":"VHDL","score":0.8820872902870178},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.7921767234802246},{"id":"https://openalex.org/keywords/computer-architecture","display_name":"Computer architecture","score":0.6478943824768066},{"id":"https://openalex.org/keywords/architecture","display_name":"Architecture","score":0.6181381940841675},{"id":"https://openalex.org/keywords/hardware-description-language","display_name":"Hardware description language","score":0.6025047302246094},{"id":"https://openalex.org/keywords/process","display_name":"Process (computing)","score":0.5600980520248413},{"id":"https://openalex.org/keywords/set","display_name":"Set (abstract data type)","score":0.5273937582969666},{"id":"https://openalex.org/keywords/programming-language","display_name":"Programming language","score":0.5109195113182068},{"id":"https://openalex.org/keywords/software-engineering","display_name":"Software engineering","score":0.4908679127693176},{"id":"https://openalex.org/keywords/architectural-model","display_name":"Architectural model","score":0.4369225800037384},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.2523156702518463},{"id":"https://openalex.org/keywords/field-programmable-gate-array","display_name":"Field-programmable gate array","score":0.17709511518478394}],"concepts":[{"id":"https://openalex.org/C36941000","wikidata":"https://www.wikidata.org/wiki/Q209455","display_name":"VHDL","level":3,"score":0.8820872902870178},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.7921767234802246},{"id":"https://openalex.org/C118524514","wikidata":"https://www.wikidata.org/wiki/Q173212","display_name":"Computer architecture","level":1,"score":0.6478943824768066},{"id":"https://openalex.org/C123657996","wikidata":"https://www.wikidata.org/wiki/Q12271","display_name":"Architecture","level":2,"score":0.6181381940841675},{"id":"https://openalex.org/C42143788","wikidata":"https://www.wikidata.org/wiki/Q173341","display_name":"Hardware description language","level":3,"score":0.6025047302246094},{"id":"https://openalex.org/C98045186","wikidata":"https://www.wikidata.org/wiki/Q205663","display_name":"Process (computing)","level":2,"score":0.5600980520248413},{"id":"https://openalex.org/C177264268","wikidata":"https://www.wikidata.org/wiki/Q1514741","display_name":"Set (abstract data type)","level":2,"score":0.5273937582969666},{"id":"https://openalex.org/C199360897","wikidata":"https://www.wikidata.org/wiki/Q9143","display_name":"Programming language","level":1,"score":0.5109195113182068},{"id":"https://openalex.org/C115903868","wikidata":"https://www.wikidata.org/wiki/Q80993","display_name":"Software engineering","level":1,"score":0.4908679127693176},{"id":"https://openalex.org/C2778544944","wikidata":"https://www.wikidata.org/wiki/Q1352349","display_name":"Architectural model","level":3,"score":0.4369225800037384},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.2523156702518463},{"id":"https://openalex.org/C42935608","wikidata":"https://www.wikidata.org/wiki/Q190411","display_name":"Field-programmable gate array","level":2,"score":0.17709511518478394},{"id":"https://openalex.org/C153349607","wikidata":"https://www.wikidata.org/wiki/Q36649","display_name":"Visual arts","level":1,"score":0.0},{"id":"https://openalex.org/C142362112","wikidata":"https://www.wikidata.org/wiki/Q735","display_name":"Art","level":0,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/iccd.1991.139865","is_oa":false,"landing_page_url":"https://doi.org/10.1109/iccd.1991.139865","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"[1991 Proceedings] IEEE International Conference on Computer Design: VLSI in Computers and Processors","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[{"display_name":"Industry, innovation and infrastructure","score":0.4099999964237213,"id":"https://metadata.un.org/sdg/9"}],"awards":[],"funders":[{"id":"https://openalex.org/F4320310536","display_name":"University of Virginia","ror":"https://ror.org/0153tk833"},{"id":"https://openalex.org/F4320332180","display_name":"Defense Advanced Research Projects Agency","ror":"https://ror.org/02caytj08"}],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":1,"referenced_works":["https://openalex.org/W26506888"],"related_works":["https://openalex.org/W2110818533","https://openalex.org/W1917852300","https://openalex.org/W2384838054","https://openalex.org/W2139058049","https://openalex.org/W2376018793","https://openalex.org/W2548456620","https://openalex.org/W2911649771","https://openalex.org/W2148697719","https://openalex.org/W2122949436","https://openalex.org/W78782492"],"abstract_inverted_index":{"A":[0],"novel":[1],"methodology":[2,16,54],"is":[3,75,78],"presented":[4],"which":[5,29,77],"allows":[6],"the":[7,18,32,47,53,59,64,72,85,100,112],"creation":[8],"of":[9,13,34,46,63,71,87],"implementation-independent":[10,69],"functional":[11],"models":[12],"systems.":[14],"The":[15,50,102],"uses":[17],"VHSIC":[19],"(very":[20],"high":[21],"speed":[22],"integrated":[23],"circuit)":[24],"hardware":[25],"description":[26],"language":[27],"(VHDL)":[28],"leads":[30],"to":[31,56],"possibility":[33],"creating":[35],"a":[36,81],"unified":[37],"design":[38,48],"environment":[39],"supporting":[40],"system":[41],"modeling":[42],"at":[43],"various":[44],"stages":[45],"process.":[49],"motivation":[51],"for":[52,111],"was":[55],"assist":[57],"in":[58,84],"analysis":[60],"and":[61],"specification":[62,110],"WM":[65,73,113],"computer":[66],"architecture.":[67],"An":[68],"model":[70,103],"architecture":[74],"provided":[76],"intended":[79],"as":[80,107],"first":[82],"step":[83],"development":[86],"an":[88,108],"implementation.":[89],"Additionally,":[90],"architectural":[91,109],"performance":[92],"measures":[93],"can":[94,104],"be":[95],"extracted":[96],"from":[97],"simulations":[98],"using":[99],"model.":[101],"also":[105],"serve":[106],"computer.<":[114],"<ETX":[115],"xmlns:mml=\"http://www.w3.org/1998/Math/MathML\"":[116],"xmlns:xlink=\"http://www.w3.org/1999/xlink\">&gt;</ETX>":[117]},"counts_by_year":[],"updated_date":"2025-11-06T03:46:38.306776","created_date":"2025-10-10T00:00:00"}