{"id":"https://openalex.org/W1994369951","doi":"https://doi.org/10.1109/icacci.2014.6968437","title":"Design and analysis of program counter using finite state machine and incrementer based logic","display_name":"Design and analysis of program counter using finite state machine and incrementer based logic","publication_year":2014,"publication_date":"2014-09-01","ids":{"openalex":"https://openalex.org/W1994369951","doi":"https://doi.org/10.1109/icacci.2014.6968437","mag":"1994369951"},"language":"en","primary_location":{"id":"doi:10.1109/icacci.2014.6968437","is_oa":false,"landing_page_url":"https://doi.org/10.1109/icacci.2014.6968437","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2014 International Conference on Advances in Computing, Communications and Informatics (ICACCI)","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5020006903","display_name":"Marichamy Divya","orcid":"https://orcid.org/0000-0003-1007-7733"},"institutions":[{"id":"https://openalex.org/I876193797","display_name":"Vellore Institute of Technology University","ror":"https://ror.org/00qzypv28","country_code":"IN","type":"education","lineage":["https://openalex.org/I876193797"]}],"countries":["IN"],"is_corresponding":true,"raw_author_name":"M. Divya","raw_affiliation_strings":["School of Electronics Engineering, VIT University, Chennai, Tamil Nadu, India","School of Electronics Engineering VIT University Chennai Tamil Nadu India"],"affiliations":[{"raw_affiliation_string":"School of Electronics Engineering, VIT University, Chennai, Tamil Nadu, India","institution_ids":["https://openalex.org/I876193797"]},{"raw_affiliation_string":"School of Electronics Engineering VIT University Chennai Tamil Nadu India","institution_ids":["https://openalex.org/I876193797"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5051697565","display_name":"Ritesh Belgudri","orcid":null},"institutions":[{"id":"https://openalex.org/I876193797","display_name":"Vellore Institute of Technology University","ror":"https://ror.org/00qzypv28","country_code":"IN","type":"education","lineage":["https://openalex.org/I876193797"]}],"countries":["IN"],"is_corresponding":false,"raw_author_name":"Ritesh Belgudri","raw_affiliation_strings":["School of Electronics Engineering, VIT University, Chennai, Tamil Nadu, India","School of Electronics Engineering VIT University Chennai Tamil Nadu India"],"affiliations":[{"raw_affiliation_string":"School of Electronics Engineering, VIT University, Chennai, Tamil Nadu, India","institution_ids":["https://openalex.org/I876193797"]},{"raw_affiliation_string":"School of Electronics Engineering VIT University Chennai Tamil Nadu India","institution_ids":["https://openalex.org/I876193797"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5030426808","display_name":"V. S. Kanchana Bhaaskaran","orcid":"https://orcid.org/0000-0002-3819-1952"},"institutions":[{"id":"https://openalex.org/I876193797","display_name":"Vellore Institute of Technology University","ror":"https://ror.org/00qzypv28","country_code":"IN","type":"education","lineage":["https://openalex.org/I876193797"]}],"countries":["IN"],"is_corresponding":false,"raw_author_name":"V.S. Kanchana Bhaaskaran","raw_affiliation_strings":["School of Electronics Engineering, VIT University, Vellore, Tamil Nadu, IN","School of Electronics Engineering VIT University Chennai Tamil Nadu India"],"affiliations":[{"raw_affiliation_string":"School of Electronics Engineering, VIT University, Vellore, Tamil Nadu, IN","institution_ids":["https://openalex.org/I876193797"]},{"raw_affiliation_string":"School of Electronics Engineering VIT University Chennai Tamil Nadu India","institution_ids":["https://openalex.org/I876193797"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":3,"corresponding_author_ids":["https://openalex.org/A5020006903"],"corresponding_institution_ids":["https://openalex.org/I876193797"],"apc_list":null,"apc_paid":null,"fwci":0.2093,"has_fulltext":false,"cited_by_count":2,"citation_normalized_percentile":{"value":0.57169194,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":90,"max":94},"biblio":{"volume":"2","issue":null,"first_page":"581","last_page":"587"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T13182","display_name":"Quantum-Dot Cellular Automata","score":0.9995999932289124,"subfield":{"id":"https://openalex.org/subfields/1703","display_name":"Computational Theory and Mathematics"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10323","display_name":"Analog and Mixed-Signal Circuit Design","score":0.9980000257492065,"subfield":{"id":"https://openalex.org/subfields/2204","display_name":"Biomedical Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/finite-state-machine","display_name":"Finite-state machine","score":0.8055204153060913},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.6286888122558594},{"id":"https://openalex.org/keywords/logic-synthesis","display_name":"Logic synthesis","score":0.6264219284057617},{"id":"https://openalex.org/keywords/multiplexer","display_name":"Multiplexer","score":0.6212458610534668},{"id":"https://openalex.org/keywords/sequential-logic","display_name":"Sequential logic","score":0.5973553657531738},{"id":"https://openalex.org/keywords/state","display_name":"State (computer science)","score":0.5554439425468445},{"id":"https://openalex.org/keywords/logic-optimization","display_name":"Logic optimization","score":0.5264281034469604},{"id":"https://openalex.org/keywords/computer-engineering","display_name":"Computer engineering","score":0.5105403661727905},{"id":"https://openalex.org/keywords/logic-gate","display_name":"Logic gate","score":0.4888250231742859},{"id":"https://openalex.org/keywords/cadence","display_name":"Cadence","score":0.4676862359046936},{"id":"https://openalex.org/keywords/logic-family","display_name":"Logic family","score":0.4423344135284424},{"id":"https://openalex.org/keywords/algorithm","display_name":"Algorithm","score":0.3379783630371094},{"id":"https://openalex.org/keywords/arithmetic","display_name":"Arithmetic","score":0.3337879776954651},{"id":"https://openalex.org/keywords/electronic-engineering","display_name":"Electronic engineering","score":0.2468576431274414},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.2266159951686859},{"id":"https://openalex.org/keywords/mathematics","display_name":"Mathematics","score":0.2028711438179016},{"id":"https://openalex.org/keywords/multiplexing","display_name":"Multiplexing","score":0.09579610824584961},{"id":"https://openalex.org/keywords/telecommunications","display_name":"Telecommunications","score":0.07999038696289062}],"concepts":[{"id":"https://openalex.org/C167822520","wikidata":"https://www.wikidata.org/wiki/Q176452","display_name":"Finite-state machine","level":2,"score":0.8055204153060913},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.6286888122558594},{"id":"https://openalex.org/C157922185","wikidata":"https://www.wikidata.org/wiki/Q173198","display_name":"Logic synthesis","level":3,"score":0.6264219284057617},{"id":"https://openalex.org/C70970002","wikidata":"https://www.wikidata.org/wiki/Q189434","display_name":"Multiplexer","level":3,"score":0.6212458610534668},{"id":"https://openalex.org/C187075797","wikidata":"https://www.wikidata.org/wiki/Q173245","display_name":"Sequential logic","level":3,"score":0.5973553657531738},{"id":"https://openalex.org/C48103436","wikidata":"https://www.wikidata.org/wiki/Q599031","display_name":"State (computer science)","level":2,"score":0.5554439425468445},{"id":"https://openalex.org/C28449271","wikidata":"https://www.wikidata.org/wiki/Q6667469","display_name":"Logic optimization","level":4,"score":0.5264281034469604},{"id":"https://openalex.org/C113775141","wikidata":"https://www.wikidata.org/wiki/Q428691","display_name":"Computer engineering","level":1,"score":0.5105403661727905},{"id":"https://openalex.org/C131017901","wikidata":"https://www.wikidata.org/wiki/Q170451","display_name":"Logic gate","level":2,"score":0.4888250231742859},{"id":"https://openalex.org/C2777125575","wikidata":"https://www.wikidata.org/wiki/Q14088448","display_name":"Cadence","level":2,"score":0.4676862359046936},{"id":"https://openalex.org/C162454741","wikidata":"https://www.wikidata.org/wiki/Q173359","display_name":"Logic family","level":4,"score":0.4423344135284424},{"id":"https://openalex.org/C11413529","wikidata":"https://www.wikidata.org/wiki/Q8366","display_name":"Algorithm","level":1,"score":0.3379783630371094},{"id":"https://openalex.org/C94375191","wikidata":"https://www.wikidata.org/wiki/Q11205","display_name":"Arithmetic","level":1,"score":0.3337879776954651},{"id":"https://openalex.org/C24326235","wikidata":"https://www.wikidata.org/wiki/Q126095","display_name":"Electronic engineering","level":1,"score":0.2468576431274414},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.2266159951686859},{"id":"https://openalex.org/C33923547","wikidata":"https://www.wikidata.org/wiki/Q395","display_name":"Mathematics","level":0,"score":0.2028711438179016},{"id":"https://openalex.org/C19275194","wikidata":"https://www.wikidata.org/wiki/Q222903","display_name":"Multiplexing","level":2,"score":0.09579610824584961},{"id":"https://openalex.org/C76155785","wikidata":"https://www.wikidata.org/wiki/Q418","display_name":"Telecommunications","level":1,"score":0.07999038696289062}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/icacci.2014.6968437","is_oa":false,"landing_page_url":"https://doi.org/10.1109/icacci.2014.6968437","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2014 International Conference on Advances in Computing, Communications and Informatics (ICACCI)","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[],"awards":[],"funders":[],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":13,"referenced_works":["https://openalex.org/W1533030620","https://openalex.org/W1555915743","https://openalex.org/W1582900148","https://openalex.org/W1779546914","https://openalex.org/W2044956499","https://openalex.org/W2121454685","https://openalex.org/W2150554872","https://openalex.org/W2316374814","https://openalex.org/W2541574209","https://openalex.org/W2725179571","https://openalex.org/W3145830094","https://openalex.org/W6633127185","https://openalex.org/W6635027031"],"related_works":["https://openalex.org/W3129977055","https://openalex.org/W1966764473","https://openalex.org/W1488117239","https://openalex.org/W2386022279","https://openalex.org/W659242671","https://openalex.org/W2356140560","https://openalex.org/W2051956260","https://openalex.org/W2356714888","https://openalex.org/W2159017686","https://openalex.org/W1497518879"],"abstract_inverted_index":{"The":[0,32,48,71,100,130],"paper":[1],"presents":[2],"the":[3,6,38,41,61,66,76,104,115,123,128],"design":[4,43,54,64,94,107],"of":[5,91,114,125],"program":[7,77],"counter":[8,78],"for":[9],"low":[10],"power":[11,73],"and":[12,24,37,58,69,144],"high":[13],"performance.":[14],"Two":[15],"approaches":[16],"namely,":[17],"1)":[18],"finite":[19,49,116],"state":[20,50,117],"machine":[21,51,118],"logic":[22,28,52,83],"based":[23,27,53,63,82,93,106,119],"2)":[25],"incrementer":[26,62,67,105],"have":[29,34,132],"been":[30,35,46,133],"employed.":[31],"designs":[33,131],"implemented":[36,134],"comparison":[39],"between":[40],"two":[42],"methodologies":[44],"has":[45],"made.":[47],"uses":[55],"flip":[56],"flops":[57],"multiplexers,":[59],"while":[60],"employs":[65],"circuit":[68],"registers.":[70],"average":[72],"consumed":[74],"by":[75,103],"designed":[79],"using":[80,135,146],"FSM":[81],"is":[84,108],"64.72%":[85],"less":[86],"as":[87],"compared":[88,111],"to":[89,112],"that":[90,113],"Incrementer":[92],"at":[95,122],"1":[96],"GHz":[97],"operation":[98],"frequency.":[99],"delay":[101],"incurred":[102],"34.92%":[109],"lesser":[110],"approach,":[120],"however":[121],"cost":[124],"increase":[126],"in":[127],"area.":[129],"industry":[136],"standard":[137],"Cadence":[138],"<sup":[139],"xmlns:mml=\"http://www.w3.org/1998/Math/MathML\"":[140],"xmlns:xlink=\"http://www.w3.org/1999/xlink\">\u00ae</sup>":[141],"EDA":[142],"tools":[143],"simulated":[145],"90nm":[147],"technology":[148],"files.":[149]},"counts_by_year":[{"year":2019,"cited_by_count":1},{"year":2017,"cited_by_count":1}],"updated_date":"2025-11-06T03:46:38.306776","created_date":"2025-10-10T00:00:00"}
