{"id":"https://openalex.org/W2972646979","doi":"https://doi.org/10.1109/i2mtc.2019.8826927","title":"Time-to-Digital Converter with Pseudo-Segmented Delay Line","display_name":"Time-to-Digital Converter with Pseudo-Segmented Delay Line","publication_year":2019,"publication_date":"2019-05-01","ids":{"openalex":"https://openalex.org/W2972646979","doi":"https://doi.org/10.1109/i2mtc.2019.8826927","mag":"2972646979"},"language":"en","primary_location":{"id":"doi:10.1109/i2mtc.2019.8826927","is_oa":false,"landing_page_url":"https://doi.org/10.1109/i2mtc.2019.8826927","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2019 IEEE International Instrumentation and Measurement Technology Conference (I2MTC)","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5010527189","display_name":"Pawe\u0142 Kwiatkowski","orcid":"https://orcid.org/0000-0001-5744-5981"},"institutions":[{"id":"https://openalex.org/I2800249161","display_name":"Military University of Technology in Warsaw","ror":"https://ror.org/05fct5h31","country_code":"PL","type":"education","lineage":["https://openalex.org/I2800249161"]}],"countries":["PL"],"is_corresponding":true,"raw_author_name":"P. Kwiatkowski","raw_affiliation_strings":["Department of Electronics, Military University of Technology, Warsaw, Poland"],"affiliations":[{"raw_affiliation_string":"Department of Electronics, Military University of Technology, Warsaw, Poland","institution_ids":["https://openalex.org/I2800249161"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5038829239","display_name":"R. Szplet","orcid":"https://orcid.org/0000-0003-3085-013X"},"institutions":[{"id":"https://openalex.org/I2800249161","display_name":"Military University of Technology in Warsaw","ror":"https://ror.org/05fct5h31","country_code":"PL","type":"education","lineage":["https://openalex.org/I2800249161"]}],"countries":["PL"],"is_corresponding":false,"raw_author_name":"R. Szplet","raw_affiliation_strings":["Department of Electronics, Military University of Technology, Warsaw, Poland"],"affiliations":[{"raw_affiliation_string":"Department of Electronics, Military University of Technology, Warsaw, Poland","institution_ids":["https://openalex.org/I2800249161"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":2,"corresponding_author_ids":["https://openalex.org/A5010527189"],"corresponding_institution_ids":["https://openalex.org/I2800249161"],"apc_list":null,"apc_paid":null,"fwci":0.3577,"has_fulltext":false,"cited_by_count":6,"citation_normalized_percentile":{"value":0.61129368,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":89,"max":96},"biblio":{"volume":"24","issue":null,"first_page":"1","last_page":"6"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T11417","display_name":"Advancements in PLL and VCO Technologies","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T11417","display_name":"Advancements in PLL and VCO Technologies","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10323","display_name":"Analog and Mixed-Signal Circuit Design","score":0.998199999332428,"subfield":{"id":"https://openalex.org/subfields/2204","display_name":"Biomedical Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T12216","display_name":"Network Time Synchronization Technologies","score":0.9925000071525574,"subfield":{"id":"https://openalex.org/subfields/1705","display_name":"Computer Networks and Communications"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/field-programmable-gate-array","display_name":"Field-programmable gate array","score":0.8398228883743286},{"id":"https://openalex.org/keywords/time-to-digital-converter","display_name":"Time-to-digital converter","score":0.7510831952095032},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.6753963232040405},{"id":"https://openalex.org/keywords/timestamp","display_name":"Timestamp","score":0.555359423160553},{"id":"https://openalex.org/keywords/computer-hardware","display_name":"Computer hardware","score":0.5304065942764282},{"id":"https://openalex.org/keywords/electronic-engineering","display_name":"Electronic engineering","score":0.4735402464866638},{"id":"https://openalex.org/keywords/digital-clock-manager","display_name":"Digital clock manager","score":0.4565751552581787},{"id":"https://openalex.org/keywords/delay-calculation","display_name":"Delay calculation","score":0.4470215439796448},{"id":"https://openalex.org/keywords/coding","display_name":"Coding (social sciences)","score":0.43516626954078674},{"id":"https://openalex.org/keywords/system-time","display_name":"System time","score":0.4330011010169983},{"id":"https://openalex.org/keywords/line","display_name":"Line (geometry)","score":0.4193270206451416},{"id":"https://openalex.org/keywords/gate-array","display_name":"Gate array","score":0.4158465266227722},{"id":"https://openalex.org/keywords/propagation-delay","display_name":"Propagation delay","score":0.4111422896385193},{"id":"https://openalex.org/keywords/real-time-computing","display_name":"Real-time computing","score":0.28886348009109497},{"id":"https://openalex.org/keywords/synchronous-circuit","display_name":"Synchronous circuit","score":0.21388331055641174},{"id":"https://openalex.org/keywords/clock-signal","display_name":"Clock signal","score":0.2081541121006012},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.18996989727020264},{"id":"https://openalex.org/keywords/cmos","display_name":"CMOS","score":0.1891549825668335},{"id":"https://openalex.org/keywords/jitter","display_name":"Jitter","score":0.11871680617332458}],"concepts":[{"id":"https://openalex.org/C42935608","wikidata":"https://www.wikidata.org/wiki/Q190411","display_name":"Field-programmable gate array","level":2,"score":0.8398228883743286},{"id":"https://openalex.org/C99594498","wikidata":"https://www.wikidata.org/wiki/Q2434524","display_name":"Time-to-digital converter","level":4,"score":0.7510831952095032},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.6753963232040405},{"id":"https://openalex.org/C113954288","wikidata":"https://www.wikidata.org/wiki/Q186885","display_name":"Timestamp","level":2,"score":0.555359423160553},{"id":"https://openalex.org/C9390403","wikidata":"https://www.wikidata.org/wiki/Q3966","display_name":"Computer hardware","level":1,"score":0.5304065942764282},{"id":"https://openalex.org/C24326235","wikidata":"https://www.wikidata.org/wiki/Q126095","display_name":"Electronic engineering","level":1,"score":0.4735402464866638},{"id":"https://openalex.org/C113074038","wikidata":"https://www.wikidata.org/wiki/Q5276052","display_name":"Digital clock manager","level":5,"score":0.4565751552581787},{"id":"https://openalex.org/C174086752","wikidata":"https://www.wikidata.org/wiki/Q5253471","display_name":"Delay calculation","level":3,"score":0.4470215439796448},{"id":"https://openalex.org/C179518139","wikidata":"https://www.wikidata.org/wiki/Q5140297","display_name":"Coding (social sciences)","level":2,"score":0.43516626954078674},{"id":"https://openalex.org/C192082776","wikidata":"https://www.wikidata.org/wiki/Q7663751","display_name":"System time","level":3,"score":0.4330011010169983},{"id":"https://openalex.org/C198352243","wikidata":"https://www.wikidata.org/wiki/Q37105","display_name":"Line (geometry)","level":2,"score":0.4193270206451416},{"id":"https://openalex.org/C114237110","wikidata":"https://www.wikidata.org/wiki/Q114901","display_name":"Gate array","level":3,"score":0.4158465266227722},{"id":"https://openalex.org/C90806461","wikidata":"https://www.wikidata.org/wiki/Q1144416","display_name":"Propagation delay","level":2,"score":0.4111422896385193},{"id":"https://openalex.org/C79403827","wikidata":"https://www.wikidata.org/wiki/Q3988","display_name":"Real-time computing","level":1,"score":0.28886348009109497},{"id":"https://openalex.org/C42196554","wikidata":"https://www.wikidata.org/wiki/Q1186179","display_name":"Synchronous circuit","level":4,"score":0.21388331055641174},{"id":"https://openalex.org/C137059387","wikidata":"https://www.wikidata.org/wiki/Q426882","display_name":"Clock signal","level":3,"score":0.2081541121006012},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.18996989727020264},{"id":"https://openalex.org/C46362747","wikidata":"https://www.wikidata.org/wiki/Q173431","display_name":"CMOS","level":2,"score":0.1891549825668335},{"id":"https://openalex.org/C134652429","wikidata":"https://www.wikidata.org/wiki/Q1052698","display_name":"Jitter","level":2,"score":0.11871680617332458},{"id":"https://openalex.org/C105795698","wikidata":"https://www.wikidata.org/wiki/Q12483","display_name":"Statistics","level":1,"score":0.0},{"id":"https://openalex.org/C31258907","wikidata":"https://www.wikidata.org/wiki/Q1301371","display_name":"Computer network","level":1,"score":0.0},{"id":"https://openalex.org/C33923547","wikidata":"https://www.wikidata.org/wiki/Q395","display_name":"Mathematics","level":0,"score":0.0},{"id":"https://openalex.org/C2524010","wikidata":"https://www.wikidata.org/wiki/Q8087","display_name":"Geometry","level":1,"score":0.0},{"id":"https://openalex.org/C76155785","wikidata":"https://www.wikidata.org/wiki/Q418","display_name":"Telecommunications","level":1,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/i2mtc.2019.8826927","is_oa":false,"landing_page_url":"https://doi.org/10.1109/i2mtc.2019.8826927","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2019 IEEE International Instrumentation and Measurement Technology Conference (I2MTC)","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[],"awards":[],"funders":[],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":23,"referenced_works":["https://openalex.org/W1580704319","https://openalex.org/W1992215034","https://openalex.org/W1994429758","https://openalex.org/W2033018470","https://openalex.org/W2058219946","https://openalex.org/W2104114375","https://openalex.org/W2109553293","https://openalex.org/W2111146745","https://openalex.org/W2117966934","https://openalex.org/W2150783292","https://openalex.org/W2163805454","https://openalex.org/W2204691460","https://openalex.org/W2287634627","https://openalex.org/W2330345634","https://openalex.org/W2333526015","https://openalex.org/W2469812164","https://openalex.org/W2494646569","https://openalex.org/W2498150460","https://openalex.org/W2598216069","https://openalex.org/W2753663502","https://openalex.org/W2773611323","https://openalex.org/W2810207282","https://openalex.org/W7048679210"],"related_works":["https://openalex.org/W3015599398","https://openalex.org/W2188730438","https://openalex.org/W2792778858","https://openalex.org/W2157230896","https://openalex.org/W2034656493","https://openalex.org/W2362904186","https://openalex.org/W2114232017","https://openalex.org/W1997308464","https://openalex.org/W2040679505","https://openalex.org/W1986294008"],"abstract_inverted_index":{"This":[0],"paper":[1],"presents":[2],"a":[3,26],"time-to-digital":[4],"converter":[5],"(TDC)":[6],"with":[7],"pseudo-segmented":[8],"delay":[9,30],"line":[10,31],"implemented":[11],"in":[12,65,72],"28":[13],"nm":[14],"field-programmable":[15],"gate":[16],"array":[17],"(FPGA)":[18],"device":[19],"(Kintex-7":[20],"XC7K160T,":[21],"Xilinx).":[22],"The":[23,68],"TDC":[24,69],"employs":[25],"carry":[27],"chain":[28],"based":[29,74],"wherein":[32],"each":[33],"tap":[34],"is":[35],"connected":[36],"to":[37,60],"multiple":[38,53],"flip-flops.":[39],"Proposed":[40],"solution":[41],"gives":[42],"the":[43],"same":[44],"measurement":[45],"resolution":[46,87],"and":[47,83,88],"comparable":[48],"precision":[49],"improvement":[50],"as":[51],"using":[52],"time":[54,75],"coding":[55],"lines":[56],"(TCL)":[57],"but":[58],"allows":[59],"save":[61],"logical":[62],"resources":[63],"available":[64],"FPGA":[66],"chip.":[67],"was":[70],"tested":[71],"timestamps":[73],"interval":[76],"counter":[77],"operating":[78],"at":[79],"700":[80],"MHz":[81],"clock":[82],"provides":[84],"1.1":[85],"ps":[86,90],"5":[89],"precision.":[91]},"counts_by_year":[{"year":2025,"cited_by_count":1},{"year":2024,"cited_by_count":2},{"year":2021,"cited_by_count":1},{"year":2020,"cited_by_count":1},{"year":2019,"cited_by_count":1}],"updated_date":"2025-11-06T03:46:38.306776","created_date":"2025-10-10T00:00:00"}
