{"id":"https://openalex.org/W4200372727","doi":"https://doi.org/10.1109/hpec49654.2021.9622835","title":"Design of Asynchronous Polymorphic Logic Gates for Hardware Security","display_name":"Design of Asynchronous Polymorphic Logic Gates for Hardware Security","publication_year":2021,"publication_date":"2021-09-20","ids":{"openalex":"https://openalex.org/W4200372727","doi":"https://doi.org/10.1109/hpec49654.2021.9622835"},"language":"en","primary_location":{"id":"doi:10.1109/hpec49654.2021.9622835","is_oa":false,"landing_page_url":"https://doi.org/10.1109/hpec49654.2021.9622835","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2021 IEEE High Performance Extreme Computing Conference (HPEC)","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5091320900","display_name":"Chandler Bernard","orcid":null},"institutions":[{"id":"https://openalex.org/I78715868","display_name":"University of Arkansas at Fayetteville","ror":"https://ror.org/05jbt9m15","country_code":"US","type":"education","lineage":["https://openalex.org/I78715868"]}],"countries":["US"],"is_corresponding":true,"raw_author_name":"Chandler Bernard","raw_affiliation_strings":["University of Arkansas, Fayetteville, AR, USA"],"affiliations":[{"raw_affiliation_string":"University of Arkansas, Fayetteville, AR, USA","institution_ids":["https://openalex.org/I78715868"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5027517382","display_name":"William F. Bryant","orcid":null},"institutions":[{"id":"https://openalex.org/I78715868","display_name":"University of Arkansas at Fayetteville","ror":"https://ror.org/05jbt9m15","country_code":"US","type":"education","lineage":["https://openalex.org/I78715868"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"William Bryant","raw_affiliation_strings":["University of Arkansas, Fayetteville, AR, USA"],"affiliations":[{"raw_affiliation_string":"University of Arkansas, Fayetteville, AR, USA","institution_ids":["https://openalex.org/I78715868"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5103482706","display_name":"Richard A. Becker","orcid":null},"institutions":[{"id":"https://openalex.org/I78715868","display_name":"University of Arkansas at Fayetteville","ror":"https://ror.org/05jbt9m15","country_code":"US","type":"education","lineage":["https://openalex.org/I78715868"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Richard Becker","raw_affiliation_strings":["University of Arkansas, Fayetteville, AR, USA"],"affiliations":[{"raw_affiliation_string":"University of Arkansas, Fayetteville, AR, USA","institution_ids":["https://openalex.org/I78715868"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5101644887","display_name":"Jia Di","orcid":"https://orcid.org/0000-0001-7718-0220"},"institutions":[{"id":"https://openalex.org/I78715868","display_name":"University of Arkansas at Fayetteville","ror":"https://ror.org/05jbt9m15","country_code":"US","type":"education","lineage":["https://openalex.org/I78715868"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Jia Di","raw_affiliation_strings":["University of Arkansas, Fayetteville, AR, USA"],"affiliations":[{"raw_affiliation_string":"University of Arkansas, Fayetteville, AR, USA","institution_ids":["https://openalex.org/I78715868"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":4,"corresponding_author_ids":["https://openalex.org/A5091320900"],"corresponding_institution_ids":["https://openalex.org/I78715868"],"apc_list":null,"apc_paid":null,"fwci":0.6798,"has_fulltext":false,"cited_by_count":8,"citation_normalized_percentile":{"value":0.76560667,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":94,"max":97},"biblio":{"volume":null,"issue":null,"first_page":"1","last_page":"5"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T11975","display_name":"Evolutionary Algorithms and Applications","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/1702","display_name":"Artificial Intelligence"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T11975","display_name":"Evolutionary Algorithms and Applications","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/1702","display_name":"Artificial Intelligence"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":0.9969000220298767,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11522","display_name":"VLSI and FPGA Design Techniques","score":0.9937000274658203,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/asynchronous-communication","display_name":"Asynchronous communication","score":0.7908889055252075},{"id":"https://openalex.org/keywords/reconfigurability","display_name":"Reconfigurability","score":0.7797147035598755},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.6665626764297485},{"id":"https://openalex.org/keywords/field-programmable-gate-array","display_name":"Field-programmable gate array","score":0.6497255563735962},{"id":"https://openalex.org/keywords/asynchronous-circuit","display_name":"Asynchronous circuit","score":0.6265219449996948},{"id":"https://openalex.org/keywords/logic-gate","display_name":"Logic gate","score":0.6223082542419434},{"id":"https://openalex.org/keywords/logic-synthesis","display_name":"Logic synthesis","score":0.5603832602500916},{"id":"https://openalex.org/keywords/electronic-circuit","display_name":"Electronic circuit","score":0.4783320426940918},{"id":"https://openalex.org/keywords/programmable-logic-array","display_name":"Programmable logic array","score":0.446575790643692},{"id":"https://openalex.org/keywords/logic-family","display_name":"Logic family","score":0.4399590492248535},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.4166123569011688},{"id":"https://openalex.org/keywords/computer-architecture","display_name":"Computer architecture","score":0.4025423526763916},{"id":"https://openalex.org/keywords/computer-hardware","display_name":"Computer hardware","score":0.39784976840019226},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.1884250044822693},{"id":"https://openalex.org/keywords/electrical-engineering","display_name":"Electrical engineering","score":0.15367862582206726},{"id":"https://openalex.org/keywords/algorithm","display_name":"Algorithm","score":0.12579959630966187},{"id":"https://openalex.org/keywords/computer-network","display_name":"Computer network","score":0.08876079320907593},{"id":"https://openalex.org/keywords/synchronous-circuit","display_name":"Synchronous circuit","score":0.08415055274963379}],"concepts":[{"id":"https://openalex.org/C151319957","wikidata":"https://www.wikidata.org/wiki/Q752739","display_name":"Asynchronous communication","level":2,"score":0.7908889055252075},{"id":"https://openalex.org/C2780149590","wikidata":"https://www.wikidata.org/wiki/Q7302742","display_name":"Reconfigurability","level":2,"score":0.7797147035598755},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.6665626764297485},{"id":"https://openalex.org/C42935608","wikidata":"https://www.wikidata.org/wiki/Q190411","display_name":"Field-programmable gate array","level":2,"score":0.6497255563735962},{"id":"https://openalex.org/C87695204","wikidata":"https://www.wikidata.org/wiki/Q629971","display_name":"Asynchronous circuit","level":5,"score":0.6265219449996948},{"id":"https://openalex.org/C131017901","wikidata":"https://www.wikidata.org/wiki/Q170451","display_name":"Logic gate","level":2,"score":0.6223082542419434},{"id":"https://openalex.org/C157922185","wikidata":"https://www.wikidata.org/wiki/Q173198","display_name":"Logic synthesis","level":3,"score":0.5603832602500916},{"id":"https://openalex.org/C134146338","wikidata":"https://www.wikidata.org/wiki/Q1815901","display_name":"Electronic circuit","level":2,"score":0.4783320426940918},{"id":"https://openalex.org/C182322920","wikidata":"https://www.wikidata.org/wiki/Q2112217","display_name":"Programmable logic array","level":3,"score":0.446575790643692},{"id":"https://openalex.org/C162454741","wikidata":"https://www.wikidata.org/wiki/Q173359","display_name":"Logic family","level":4,"score":0.4399590492248535},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.4166123569011688},{"id":"https://openalex.org/C118524514","wikidata":"https://www.wikidata.org/wiki/Q173212","display_name":"Computer architecture","level":1,"score":0.4025423526763916},{"id":"https://openalex.org/C9390403","wikidata":"https://www.wikidata.org/wiki/Q3966","display_name":"Computer hardware","level":1,"score":0.39784976840019226},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.1884250044822693},{"id":"https://openalex.org/C119599485","wikidata":"https://www.wikidata.org/wiki/Q43035","display_name":"Electrical engineering","level":1,"score":0.15367862582206726},{"id":"https://openalex.org/C11413529","wikidata":"https://www.wikidata.org/wiki/Q8366","display_name":"Algorithm","level":1,"score":0.12579959630966187},{"id":"https://openalex.org/C31258907","wikidata":"https://www.wikidata.org/wiki/Q1301371","display_name":"Computer network","level":1,"score":0.08876079320907593},{"id":"https://openalex.org/C42196554","wikidata":"https://www.wikidata.org/wiki/Q1186179","display_name":"Synchronous circuit","level":4,"score":0.08415055274963379},{"id":"https://openalex.org/C137059387","wikidata":"https://www.wikidata.org/wiki/Q426882","display_name":"Clock signal","level":3,"score":0.0},{"id":"https://openalex.org/C76155785","wikidata":"https://www.wikidata.org/wiki/Q418","display_name":"Telecommunications","level":1,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/hpec49654.2021.9622835","is_oa":false,"landing_page_url":"https://doi.org/10.1109/hpec49654.2021.9622835","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2021 IEEE High Performance Extreme Computing Conference (HPEC)","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[{"score":0.5699999928474426,"display_name":"Affordable and clean energy","id":"https://metadata.un.org/sdg/7"}],"awards":[],"funders":[],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":7,"referenced_works":["https://openalex.org/W1584355183","https://openalex.org/W2130330964","https://openalex.org/W2132597719","https://openalex.org/W2135120841","https://openalex.org/W2170580381","https://openalex.org/W2912122427","https://openalex.org/W4300138635"],"related_works":["https://openalex.org/W2139569078","https://openalex.org/W2254425074","https://openalex.org/W1512285683","https://openalex.org/W2197466303","https://openalex.org/W2170504327","https://openalex.org/W2002687983","https://openalex.org/W2526300902","https://openalex.org/W4252227487","https://openalex.org/W2132683268","https://openalex.org/W1607849496"],"abstract_inverted_index":{"Polymorphic":[0],"circuits":[1,3],"are":[2,50],"that":[4,56],"perform":[5],"two":[6],"or":[7],"more":[8],"different":[9],"functions":[10],"under":[11],"varying":[12],"operating":[13],"conditions.":[14],"This":[15],"paper":[16],"presents":[17],"dual-function":[18],"asynchronous":[19,47,74],"polymorphic":[20,34,48,75],"logic":[21],"gates":[22,35,49,76],"with":[23,52],"functionalities":[24],"selected":[25],"by":[26],"a":[27,53],"change":[28],"in":[29,43,66],"supply":[30],"voltage.":[31],"Unlike":[32],"previous":[33],"generated":[36],"using":[37,68],"an":[38],"evolutionary":[39],"approach":[40],"for":[41],"use":[42],"synchronous":[44],"circuits,":[45],"these":[46],"designed":[51,78],"deliberate":[54],"methodology":[55],"has":[57],"been":[58],"applied":[59],"across":[60],"multiple":[61],"process":[62],"nodes":[63],"and":[64,89],"verified":[65],"silicon":[67],"the":[69,86],"TSMC":[70],"65nm":[71],"process.":[72],"The":[73],"were":[77],"to":[79],"achieve":[80],"aspects":[81],"of":[82,92],"\"hidden\"":[83],"reconfigurability":[84],"without":[85],"typical":[87],"area":[88],"security":[90],"drawbacks":[91],"field-programmable":[93],"gate":[94],"array":[95],"(FPGA)":[96],"hardware":[97],"implementations.":[98]},"counts_by_year":[{"year":2025,"cited_by_count":3},{"year":2024,"cited_by_count":2},{"year":2023,"cited_by_count":3}],"updated_date":"2025-11-06T03:46:38.306776","created_date":"2025-10-10T00:00:00"}