{"id":"https://openalex.org/W3098510835","doi":"https://doi.org/10.1109/hpec43674.2020.9286221","title":"Design and Performance Evaluation of Optimizations for OpenCL FPGA Kernels","display_name":"Design and Performance Evaluation of Optimizations for OpenCL FPGA Kernels","publication_year":2020,"publication_date":"2020-09-22","ids":{"openalex":"https://openalex.org/W3098510835","doi":"https://doi.org/10.1109/hpec43674.2020.9286221","mag":"3098510835"},"language":"en","primary_location":{"id":"doi:10.1109/hpec43674.2020.9286221","is_oa":false,"landing_page_url":"https://doi.org/10.1109/hpec43674.2020.9286221","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2020 IEEE High Performance Extreme Computing Conference (HPEC)","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5004461689","display_name":"Anthony M. Cabrera","orcid":"https://orcid.org/0000-0002-6561-0382"},"institutions":[{"id":"https://openalex.org/I204465549","display_name":"Washington University in St. Louis","ror":"https://ror.org/01yc7t268","country_code":"US","type":"education","lineage":["https://openalex.org/I204465549"]}],"countries":["US"],"is_corresponding":true,"raw_author_name":"Anthony M. Cabrera","raw_affiliation_strings":["Washington University in St. Louis, St. Louis, Missouri, USA"],"affiliations":[{"raw_affiliation_string":"Washington University in St. Louis, St. Louis, Missouri, USA","institution_ids":["https://openalex.org/I204465549"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5006814645","display_name":"Roger D. Chamberlain","orcid":"https://orcid.org/0000-0002-7207-6106"},"institutions":[{"id":"https://openalex.org/I204465549","display_name":"Washington University in St. Louis","ror":"https://ror.org/01yc7t268","country_code":"US","type":"education","lineage":["https://openalex.org/I204465549"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Roger D. Chamberlain","raw_affiliation_strings":["Washington University in St. Louis, St. Louis, Missouri, USA"],"affiliations":[{"raw_affiliation_string":"Washington University in St. Louis, St. Louis, Missouri, USA","institution_ids":["https://openalex.org/I204465549"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":2,"corresponding_author_ids":["https://openalex.org/A5004461689"],"corresponding_institution_ids":["https://openalex.org/I204465549"],"apc_list":null,"apc_paid":null,"fwci":0.231,"has_fulltext":false,"cited_by_count":2,"citation_normalized_percentile":{"value":0.50261324,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":89,"max":94},"biblio":{"volume":null,"issue":null,"first_page":"1","last_page":"7"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10054","display_name":"Parallel Computing and Optimization Techniques","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10054","display_name":"Parallel Computing and Optimization Techniques","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10904","display_name":"Embedded Systems Design Techniques","score":0.9995999932289124,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11032","display_name":"VLSI and Analog Circuit Testing","score":0.9980999827384949,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.8590905070304871},{"id":"https://openalex.org/keywords/field-programmable-gate-array","display_name":"Field-programmable gate array","score":0.7886617183685303},{"id":"https://openalex.org/keywords/design-space-exploration","display_name":"Design space exploration","score":0.659674346446991},{"id":"https://openalex.org/keywords/computer-architecture","display_name":"Computer architecture","score":0.6012197732925415},{"id":"https://openalex.org/keywords/high-level-synthesis","display_name":"High-level synthesis","score":0.578208863735199},{"id":"https://openalex.org/keywords/domain","display_name":"Domain (mathematical analysis)","score":0.5612939596176147},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.5138474106788635},{"id":"https://openalex.org/keywords/reconfigurable-computing","display_name":"Reconfigurable computing","score":0.44065141677856445},{"id":"https://openalex.org/keywords/computer-hardware","display_name":"Computer hardware","score":0.3849383592605591}],"concepts":[{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.8590905070304871},{"id":"https://openalex.org/C42935608","wikidata":"https://www.wikidata.org/wiki/Q190411","display_name":"Field-programmable gate array","level":2,"score":0.7886617183685303},{"id":"https://openalex.org/C2776221188","wikidata":"https://www.wikidata.org/wiki/Q21072556","display_name":"Design space exploration","level":2,"score":0.659674346446991},{"id":"https://openalex.org/C118524514","wikidata":"https://www.wikidata.org/wiki/Q173212","display_name":"Computer architecture","level":1,"score":0.6012197732925415},{"id":"https://openalex.org/C58013763","wikidata":"https://www.wikidata.org/wiki/Q5754574","display_name":"High-level synthesis","level":3,"score":0.578208863735199},{"id":"https://openalex.org/C36503486","wikidata":"https://www.wikidata.org/wiki/Q11235244","display_name":"Domain (mathematical analysis)","level":2,"score":0.5612939596176147},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.5138474106788635},{"id":"https://openalex.org/C142962650","wikidata":"https://www.wikidata.org/wiki/Q240838","display_name":"Reconfigurable computing","level":3,"score":0.44065141677856445},{"id":"https://openalex.org/C9390403","wikidata":"https://www.wikidata.org/wiki/Q3966","display_name":"Computer hardware","level":1,"score":0.3849383592605591},{"id":"https://openalex.org/C33923547","wikidata":"https://www.wikidata.org/wiki/Q395","display_name":"Mathematics","level":0,"score":0.0},{"id":"https://openalex.org/C134306372","wikidata":"https://www.wikidata.org/wiki/Q7754","display_name":"Mathematical analysis","level":1,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/hpec43674.2020.9286221","is_oa":false,"landing_page_url":"https://doi.org/10.1109/hpec43674.2020.9286221","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2020 IEEE High Performance Extreme Computing Conference (HPEC)","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[{"display_name":"Industry, innovation and infrastructure","score":0.5299999713897705,"id":"https://metadata.un.org/sdg/9"}],"awards":[{"id":"https://openalex.org/G8553836326","display_name":null,"funder_award_id":"CNS-1763503","funder_id":"https://openalex.org/F4320306076","funder_display_name":"National Science Foundation"}],"funders":[{"id":"https://openalex.org/F4320306076","display_name":"National Science Foundation","ror":"https://ror.org/021nxhr62"}],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":17,"referenced_works":["https://openalex.org/W1686420892","https://openalex.org/W1960771887","https://openalex.org/W1964031104","https://openalex.org/W2134354173","https://openalex.org/W2472500612","https://openalex.org/W2796841328","https://openalex.org/W2799244653","https://openalex.org/W2799340985","https://openalex.org/W2915194696","https://openalex.org/W2952501651","https://openalex.org/W2954549030","https://openalex.org/W2954586490","https://openalex.org/W2962952032","https://openalex.org/W3008559426","https://openalex.org/W3013301277","https://openalex.org/W4252821989","https://openalex.org/W6637151178"],"related_works":["https://openalex.org/W4281926497","https://openalex.org/W2612099726","https://openalex.org/W1612076744","https://openalex.org/W2152074211","https://openalex.org/W2269990635","https://openalex.org/W2126857316","https://openalex.org/W2108242004","https://openalex.org/W2129019972","https://openalex.org/W4312985392","https://openalex.org/W3164085601"],"abstract_inverted_index":{"The":[0,32,52],"use":[1],"of":[2,34,76,90,143,146],"FPGAs":[3],"in":[4],"heterogeneous":[5],"systems":[6],"are":[7,27],"valuable":[8],"because":[9],"they":[10,26],"can":[11],"be":[12],"used":[13],"to":[14,18,30,63,108,126],"architect":[15],"custom":[16],"hardware":[17,54,70,78,95,131,160],"accelerate":[19],"a":[20,57,83,124,151],"particular":[21],"application":[22],"or":[23],"domain.":[24],"However,":[25],"notoriously":[28],"difficult":[29],"program.":[31],"development":[33,43],"high":[35,134],"level":[36,85,135],"synthesis":[37],"tools":[38],"like":[39],"OpenCL":[40],"make":[41],"FPGA":[42],"more":[44],"accessible,":[45],"but":[46],"not":[47],"without":[48],"its":[49,155],"own":[50],"challenges.":[51],"synthesized":[53],"comes":[55],"from":[56,116,132],"description":[58],"that":[59],"is":[60],"semantically":[61],"closer":[62],"the":[64,68,74,77,88,92,110,117,129,133,144],"application,":[65],"which":[66],"leaves":[67],"underlying":[69],"implementation":[71],"unclear.":[72],"Moreover,":[73],"interaction":[75,156],"tuning":[79],"knobs":[80],"exposed":[81],"using":[82,113],"higher":[84],"specification":[86],"increases":[87],"challenge":[89],"finding":[91],"most":[93],"performant":[94],"configuration.":[96],"In":[97],"this":[98],"work,":[99],"we":[100,138],"address":[101],"these":[102],"aforementioned":[103],"challenges":[104],"by":[105,122],"describing":[106,123],"how":[107],"approach":[109],"design":[111],"space,":[112],"both":[114],"information":[115],"literature":[118],"as":[119,121,150],"well":[120],"methodology":[125],"better":[127],"visualize":[128],"resulting":[130],"specification.":[136],"Finally,":[137],"present":[139],"an":[140],"empirical":[141],"evaluation":[142],"impact":[145],"vectorizing":[147],"data":[148],"types":[149],"tunable":[152],"knob":[153],"and":[154],"among":[157],"other":[158],"coarse-grained":[159],"knobs.":[161]},"counts_by_year":[{"year":2024,"cited_by_count":1},{"year":2021,"cited_by_count":1}],"updated_date":"2025-11-06T03:46:38.306776","created_date":"2025-10-10T00:00:00"}
