{"id":"https://openalex.org/W2505207871","doi":"https://doi.org/10.1109/hpec.2016.7761635","title":"Novel graph processor architecture, prototype system, and results","display_name":"Novel graph processor architecture, prototype system, and results","publication_year":2016,"publication_date":"2016-09-01","ids":{"openalex":"https://openalex.org/W2505207871","doi":"https://doi.org/10.1109/hpec.2016.7761635","mag":"2505207871"},"language":"en","primary_location":{"id":"doi:10.1109/hpec.2016.7761635","is_oa":false,"landing_page_url":"https://doi.org/10.1109/hpec.2016.7761635","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2016 IEEE High Performance Extreme Computing Conference (HPEC)","raw_type":"proceedings-article"},"type":"article","indexed_in":["arxiv","crossref"],"open_access":{"is_oa":true,"oa_status":"green","oa_url":"https://arxiv.org/pdf/1607.06541","any_repository_has_fulltext":true},"authorships":[{"author_position":"first","author":{"id":null,"display_name":"William S. Song","orcid":null},"institutions":[{"id":"https://openalex.org/I4210122954","display_name":"MIT Lincoln Laboratory","ror":"https://ror.org/022z6jk58","country_code":"US","type":"facility","lineage":["https://openalex.org/I4210122954","https://openalex.org/I63966007"]}],"countries":["US"],"is_corresponding":true,"raw_author_name":"William S. Song","raw_affiliation_strings":["MIT Lincoln Laboratory, Lexington, MA, USA"],"affiliations":[{"raw_affiliation_string":"MIT Lincoln Laboratory, Lexington, MA, USA","institution_ids":["https://openalex.org/I4210122954"]}]},{"author_position":"middle","author":{"id":null,"display_name":"Vitaliy Gleyzer","orcid":null},"institutions":[{"id":"https://openalex.org/I4210122954","display_name":"MIT Lincoln Laboratory","ror":"https://ror.org/022z6jk58","country_code":"US","type":"facility","lineage":["https://openalex.org/I4210122954","https://openalex.org/I63966007"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Vitaliy Gleyzer","raw_affiliation_strings":["MIT Lincoln Laboratory, Lexington, MA, USA"],"affiliations":[{"raw_affiliation_string":"MIT Lincoln Laboratory, Lexington, MA, USA","institution_ids":["https://openalex.org/I4210122954"]}]},{"author_position":"middle","author":{"id":null,"display_name":"Alexei Lomakin","orcid":null},"institutions":[{"id":"https://openalex.org/I4210122954","display_name":"MIT Lincoln Laboratory","ror":"https://ror.org/022z6jk58","country_code":"US","type":"facility","lineage":["https://openalex.org/I4210122954","https://openalex.org/I63966007"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Alexei Lomakin","raw_affiliation_strings":["MIT Lincoln Laboratory, Lexington, MA, USA"],"affiliations":[{"raw_affiliation_string":"MIT Lincoln Laboratory, Lexington, MA, USA","institution_ids":["https://openalex.org/I4210122954"]}]},{"author_position":"last","author":{"id":null,"display_name":"Jeremy Kepner","orcid":null},"institutions":[{"id":"https://openalex.org/I4210122954","display_name":"MIT Lincoln Laboratory","ror":"https://ror.org/022z6jk58","country_code":"US","type":"facility","lineage":["https://openalex.org/I4210122954","https://openalex.org/I63966007"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Jeremy Kepner","raw_affiliation_strings":["MIT Lincoln Laboratory, Lexington, MA, USA"],"affiliations":[{"raw_affiliation_string":"MIT Lincoln Laboratory, Lexington, MA, USA","institution_ids":["https://openalex.org/I4210122954"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":4,"corresponding_author_ids":[],"corresponding_institution_ids":["https://openalex.org/I4210122954"],"apc_list":null,"apc_paid":null,"fwci":1.5223,"has_fulltext":false,"cited_by_count":20,"citation_normalized_percentile":{"value":0.88329576,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":89,"max":98},"biblio":{"volume":"20","issue":null,"first_page":"1","last_page":"7"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T12292","display_name":"Graph Theory and Algorithms","score":0.9997000098228455,"subfield":{"id":"https://openalex.org/subfields/1707","display_name":"Computer Vision and Pattern Recognition"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T12292","display_name":"Graph Theory and Algorithms","score":0.9997000098228455,"subfield":{"id":"https://openalex.org/subfields/1707","display_name":"Computer Vision and Pattern Recognition"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10829","display_name":"Interconnection Networks and Systems","score":0.9977999925613403,"subfield":{"id":"https://openalex.org/subfields/1705","display_name":"Computer Networks and Communications"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10054","display_name":"Parallel Computing and Optimization Techniques","score":0.9962000250816345,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/graph","display_name":"Graph","score":0.5598999857902527},{"id":"https://openalex.org/keywords/exploit","display_name":"Exploit","score":0.48429998755455017},{"id":"https://openalex.org/keywords/wait-for-graph","display_name":"Wait-for graph","score":0.42649999260902405},{"id":"https://openalex.org/keywords/systolic-array","display_name":"Systolic array","score":0.33869999647140503},{"id":"https://openalex.org/keywords/voltage-graph","display_name":"Voltage graph","score":0.33079999685287476},{"id":"https://openalex.org/keywords/directed-graph","display_name":"Directed graph","score":0.31459999084472656},{"id":"https://openalex.org/keywords/graph-partition","display_name":"Graph partition","score":0.30079999566078186},{"id":"https://openalex.org/keywords/clique-width","display_name":"Clique-width","score":0.2989000082015991}],"concepts":[{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.7849000096321106},{"id":"https://openalex.org/C173608175","wikidata":"https://www.wikidata.org/wiki/Q232661","display_name":"Parallel computing","level":1,"score":0.6315000057220459},{"id":"https://openalex.org/C132525143","wikidata":"https://www.wikidata.org/wiki/Q141488","display_name":"Graph","level":2,"score":0.5598999857902527},{"id":"https://openalex.org/C165696696","wikidata":"https://www.wikidata.org/wiki/Q11287","display_name":"Exploit","level":2,"score":0.48429998755455017},{"id":"https://openalex.org/C106891557","wikidata":"https://www.wikidata.org/wiki/Q4148051","display_name":"Wait-for graph","level":4,"score":0.42649999260902405},{"id":"https://openalex.org/C80444323","wikidata":"https://www.wikidata.org/wiki/Q2878974","display_name":"Theoretical computer science","level":1,"score":0.3822000026702881},{"id":"https://openalex.org/C118524514","wikidata":"https://www.wikidata.org/wiki/Q173212","display_name":"Computer architecture","level":1,"score":0.36390000581741333},{"id":"https://openalex.org/C150741067","wikidata":"https://www.wikidata.org/wiki/Q2377218","display_name":"Systolic array","level":3,"score":0.33869999647140503},{"id":"https://openalex.org/C22149727","wikidata":"https://www.wikidata.org/wiki/Q7940747","display_name":"Voltage graph","level":4,"score":0.33079999685287476},{"id":"https://openalex.org/C146380142","wikidata":"https://www.wikidata.org/wiki/Q1137726","display_name":"Directed graph","level":2,"score":0.31459999084472656},{"id":"https://openalex.org/C48903430","wikidata":"https://www.wikidata.org/wiki/Q491370","display_name":"Graph partition","level":3,"score":0.30079999566078186},{"id":"https://openalex.org/C5737132","wikidata":"https://www.wikidata.org/wiki/Q1101814","display_name":"Clique-width","level":5,"score":0.2989000082015991},{"id":"https://openalex.org/C2986651925","wikidata":"https://www.wikidata.org/wiki/Q1514868","display_name":"Graph algorithms","level":3,"score":0.2978000044822693},{"id":"https://openalex.org/C2779602883","wikidata":"https://www.wikidata.org/wiki/Q15544750","display_name":"Memory architecture","level":2,"score":0.2948000133037567},{"id":"https://openalex.org/C134727501","wikidata":"https://www.wikidata.org/wiki/Q5597073","display_name":"Graph bandwidth","level":5,"score":0.28929999470710754},{"id":"https://openalex.org/C526435321","wikidata":"https://www.wikidata.org/wiki/Q1303814","display_name":"Processor design","level":2,"score":0.2879999876022339},{"id":"https://openalex.org/C2985918086","wikidata":"https://www.wikidata.org/wiki/Q232661","display_name":"Parallel architecture","level":3,"score":0.2824999988079071},{"id":"https://openalex.org/C64339825","wikidata":"https://www.wikidata.org/wiki/Q722659","display_name":"Graph property","level":5,"score":0.2687999904155731},{"id":"https://openalex.org/C88230418","wikidata":"https://www.wikidata.org/wiki/Q131476","display_name":"Graph theory","level":2,"score":0.25679999589920044},{"id":"https://openalex.org/C17169500","wikidata":"https://www.wikidata.org/wiki/Q3033506","display_name":"Null graph","level":5,"score":0.2540999948978424},{"id":"https://openalex.org/C123657996","wikidata":"https://www.wikidata.org/wiki/Q12271","display_name":"Architecture","level":2,"score":0.2540999948978424},{"id":"https://openalex.org/C97042676","wikidata":"https://www.wikidata.org/wiki/Q5597097","display_name":"Graph reduction","level":3,"score":0.25200000405311584}],"mesh":[],"locations_count":2,"locations":[{"id":"doi:10.1109/hpec.2016.7761635","is_oa":false,"landing_page_url":"https://doi.org/10.1109/hpec.2016.7761635","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2016 IEEE High Performance Extreme Computing Conference (HPEC)","raw_type":"proceedings-article"},{"id":"pmh:oai:arXiv.org:1607.06541","is_oa":true,"landing_page_url":"http://arxiv.org/abs/1607.06541","pdf_url":"https://arxiv.org/pdf/1607.06541","source":{"id":"https://openalex.org/S4306400194","display_name":"arXiv (Cornell University)","issn_l":null,"issn":null,"is_oa":true,"is_in_doaj":false,"is_core":false,"host_organization":"https://openalex.org/I205783295","host_organization_name":"Cornell University","host_organization_lineage":["https://openalex.org/I205783295"],"host_organization_lineage_names":[],"type":"repository"},"license":null,"license_id":null,"version":"submittedVersion","is_accepted":false,"is_published":false,"raw_source_name":null,"raw_type":"text"}],"best_oa_location":{"id":"pmh:oai:arXiv.org:1607.06541","is_oa":true,"landing_page_url":"http://arxiv.org/abs/1607.06541","pdf_url":"https://arxiv.org/pdf/1607.06541","source":{"id":"https://openalex.org/S4306400194","display_name":"arXiv (Cornell University)","issn_l":null,"issn":null,"is_oa":true,"is_in_doaj":false,"is_core":false,"host_organization":"https://openalex.org/I205783295","host_organization_name":"Cornell University","host_organization_lineage":["https://openalex.org/I205783295"],"host_organization_lineage_names":[],"type":"repository"},"license":null,"license_id":null,"version":"submittedVersion","is_accepted":false,"is_published":false,"raw_source_name":null,"raw_type":"text"},"sustainable_development_goals":[],"awards":[],"funders":[],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":11,"referenced_works":["https://openalex.org/W26556108","https://openalex.org/W1978979183","https://openalex.org/W1992613305","https://openalex.org/W2042541106","https://openalex.org/W2060064441","https://openalex.org/W2065607954","https://openalex.org/W2071178550","https://openalex.org/W2235832317","https://openalex.org/W2284362118","https://openalex.org/W2487177550","https://openalex.org/W4211001913"],"related_works":[],"abstract_inverted_index":{"Graph":[0],"algorithms":[1],"are":[2,15],"increasingly":[3],"used":[4],"in":[5,90],"applications":[6],"that":[7,44],"exploit":[8],"large":[9],"databases.":[10],"However,":[11],"conventional":[12,88],"processor":[13,41,79],"architectures":[14,36],"inadequate":[16],"for":[17,37],"handling":[18],"the":[19,76],"throughput":[20],"and":[21,66],"memory":[22,54],"requirements":[23],"of":[24,34,75],"graph":[25,38,49,78,91],"computation.":[26],"Lincoln":[27],"Laboratory's":[28],"graph-processor":[29],"architecture":[30],"represents":[31],"a":[32,46,52,58],"rethinking":[33],"parallel":[35],"problems.":[39],"Our":[40],"utilizes":[42],"innovations":[43],"include":[45],"sparse":[47],"matrix-based":[48],"instruction":[50],"set,":[51],"cacheless":[53],"system,":[55],"accelerator-based":[56],"architecture,":[57],"systolic":[59],"sorter,":[60],"high-bandwidth":[61],"multidimensional":[62],"toroidal":[63],"communication":[64],"network,":[65],"randomized":[67],"communications.":[68],"A":[69],"field-programmable":[70],"gate":[71],"array":[72],"(FPGA)":[73],"prototype":[74],"new":[77],"has":[80],"been":[81],"developed":[82],"with":[83],"significant":[84],"performance":[85],"enhancement":[86],"over":[87],"processors":[89],"computational":[92],"throughput.":[93]},"counts_by_year":[{"year":2023,"cited_by_count":1},{"year":2022,"cited_by_count":2},{"year":2021,"cited_by_count":4},{"year":2020,"cited_by_count":4},{"year":2019,"cited_by_count":2},{"year":2018,"cited_by_count":5},{"year":2017,"cited_by_count":2}],"updated_date":"2026-03-07T16:01:11.037858","created_date":"2016-08-23T00:00:00"}