{"id":"https://openalex.org/W2024818089","doi":"https://doi.org/10.1109/hpec.2013.6670336","title":"Accelerating sparse matrix-matrix multiplication with 3D-stacked logic-in-memory hardware","display_name":"Accelerating sparse matrix-matrix multiplication with 3D-stacked logic-in-memory hardware","publication_year":2013,"publication_date":"2013-09-01","ids":{"openalex":"https://openalex.org/W2024818089","doi":"https://doi.org/10.1109/hpec.2013.6670336","mag":"2024818089"},"language":"en","primary_location":{"id":"doi:10.1109/hpec.2013.6670336","is_oa":false,"landing_page_url":"https://doi.org/10.1109/hpec.2013.6670336","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2013 IEEE High Performance Extreme Computing Conference (HPEC)","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref","datacite"],"open_access":{"is_oa":true,"oa_status":"green","oa_url":"https://figshare.com/articles/journal_contribution/Accelerating_Sparse_Matrix-Matrix_Multiplication_with_3D-Stacked_Logic-in-Memory_Hardware/6468275","any_repository_has_fulltext":true},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5100834891","display_name":"Qiuling Zhu","orcid":null},"institutions":[{"id":"https://openalex.org/I74973139","display_name":"Carnegie Mellon University","ror":"https://ror.org/05x2bcf33","country_code":"US","type":"education","lineage":["https://openalex.org/I74973139"]}],"countries":["US"],"is_corresponding":true,"raw_author_name":"Qiuling Zhu","raw_affiliation_strings":["Dept. of Electrical and Comp. Eng., Carnegie Mellon University, Pittsburgh, PA, USA","Dept. of Electr. & Comp. Eng., Carnegie Mellon Univ., Pittsburgh, PA, USA"],"affiliations":[{"raw_affiliation_string":"Dept. of Electrical and Comp. Eng., Carnegie Mellon University, Pittsburgh, PA, USA","institution_ids":["https://openalex.org/I74973139"]},{"raw_affiliation_string":"Dept. of Electr. & Comp. Eng., Carnegie Mellon Univ., Pittsburgh, PA, USA","institution_ids":["https://openalex.org/I74973139"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5063412560","display_name":"Tobias Graf","orcid":"https://orcid.org/0000-0003-4038-147X"},"institutions":[{"id":"https://openalex.org/I74973139","display_name":"Carnegie Mellon University","ror":"https://ror.org/05x2bcf33","country_code":"US","type":"education","lineage":["https://openalex.org/I74973139"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Tobias Graf","raw_affiliation_strings":["Dept. of Electrical and Comp. Eng., Carnegie Mellon University, Pittsburgh, PA, USA","Dept. of Electr. & Comp. Eng., Carnegie Mellon Univ., Pittsburgh, PA, USA"],"affiliations":[{"raw_affiliation_string":"Dept. of Electrical and Comp. Eng., Carnegie Mellon University, Pittsburgh, PA, USA","institution_ids":["https://openalex.org/I74973139"]},{"raw_affiliation_string":"Dept. of Electr. & Comp. Eng., Carnegie Mellon Univ., Pittsburgh, PA, USA","institution_ids":["https://openalex.org/I74973139"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5003823095","display_name":"H. Ekin Sumbul","orcid":"https://orcid.org/0000-0001-6812-8033"},"institutions":[{"id":"https://openalex.org/I74973139","display_name":"Carnegie Mellon University","ror":"https://ror.org/05x2bcf33","country_code":"US","type":"education","lineage":["https://openalex.org/I74973139"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"H. Ekin Sumbul","raw_affiliation_strings":["Dept. of Electrical and Comp. Eng., Carnegie Mellon University, Pittsburgh, PA, USA","Dept. of Electr. & Comp. Eng., Carnegie Mellon Univ., Pittsburgh, PA, USA"],"affiliations":[{"raw_affiliation_string":"Dept. of Electrical and Comp. Eng., Carnegie Mellon University, Pittsburgh, PA, USA","institution_ids":["https://openalex.org/I74973139"]},{"raw_affiliation_string":"Dept. of Electr. & Comp. Eng., Carnegie Mellon Univ., Pittsburgh, PA, USA","institution_ids":["https://openalex.org/I74973139"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5033242808","display_name":"Larry Pileggi","orcid":"https://orcid.org/0000-0002-8605-8240"},"institutions":[{"id":"https://openalex.org/I74973139","display_name":"Carnegie Mellon University","ror":"https://ror.org/05x2bcf33","country_code":"US","type":"education","lineage":["https://openalex.org/I74973139"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Larry Pileggi","raw_affiliation_strings":["Dept. of Electrical and Comp. Eng., Carnegie Mellon University, Pittsburgh, PA, USA","Dept. of Electr. & Comp. Eng., Carnegie Mellon Univ., Pittsburgh, PA, USA"],"affiliations":[{"raw_affiliation_string":"Dept. of Electrical and Comp. Eng., Carnegie Mellon University, Pittsburgh, PA, USA","institution_ids":["https://openalex.org/I74973139"]},{"raw_affiliation_string":"Dept. of Electr. & Comp. Eng., Carnegie Mellon Univ., Pittsburgh, PA, USA","institution_ids":["https://openalex.org/I74973139"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5062806943","display_name":"Franz Franchetti","orcid":"https://orcid.org/0000-0002-3529-8973"},"institutions":[{"id":"https://openalex.org/I74973139","display_name":"Carnegie Mellon University","ror":"https://ror.org/05x2bcf33","country_code":"US","type":"education","lineage":["https://openalex.org/I74973139"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Franz Franchetti","raw_affiliation_strings":["Dept. of Electrical and Comp. Eng., Carnegie Mellon University, Pittsburgh, PA, USA","Dept. of Electr. & Comp. Eng., Carnegie Mellon Univ., Pittsburgh, PA, USA"],"affiliations":[{"raw_affiliation_string":"Dept. of Electrical and Comp. Eng., Carnegie Mellon University, Pittsburgh, PA, USA","institution_ids":["https://openalex.org/I74973139"]},{"raw_affiliation_string":"Dept. of Electr. & Comp. Eng., Carnegie Mellon Univ., Pittsburgh, PA, USA","institution_ids":["https://openalex.org/I74973139"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":5,"corresponding_author_ids":["https://openalex.org/A5100834891"],"corresponding_institution_ids":["https://openalex.org/I74973139"],"apc_list":null,"apc_paid":null,"fwci":6.0258,"has_fulltext":false,"cited_by_count":110,"citation_normalized_percentile":{"value":0.96184652,"is_in_top_1_percent":false,"is_in_top_10_percent":true},"cited_by_percentile_year":{"min":89,"max":100},"biblio":{"volume":null,"issue":null,"first_page":null,"last_page":null},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10054","display_name":"Parallel Computing and Optimization Techniques","score":0.9995999932289124,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10054","display_name":"Parallel Computing and Optimization Techniques","score":0.9995999932289124,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T12326","display_name":"Network Packet Processing and Optimization","score":0.9994000196456909,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10502","display_name":"Advanced Memory and Neural Computing","score":0.9987999796867371,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.7620555758476257},{"id":"https://openalex.org/keywords/dram","display_name":"Dram","score":0.7045110464096069},{"id":"https://openalex.org/keywords/sparse-matrix","display_name":"Sparse matrix","score":0.5461451411247253},{"id":"https://openalex.org/keywords/leverage","display_name":"Leverage (statistics)","score":0.5340911746025085},{"id":"https://openalex.org/keywords/computer-hardware","display_name":"Computer hardware","score":0.5273854732513428},{"id":"https://openalex.org/keywords/parallel-computing","display_name":"Parallel computing","score":0.4543125629425049},{"id":"https://openalex.org/keywords/matrix-multiplication","display_name":"Matrix multiplication","score":0.4510372281074524},{"id":"https://openalex.org/keywords/software","display_name":"Software","score":0.4330577850341797},{"id":"https://openalex.org/keywords/computer-architecture","display_name":"Computer architecture","score":0.4273565709590912},{"id":"https://openalex.org/keywords/hardware-acceleration","display_name":"Hardware acceleration","score":0.4260774254798889},{"id":"https://openalex.org/keywords/memory-bandwidth","display_name":"Memory bandwidth","score":0.41151660680770874},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.3313905894756317},{"id":"https://openalex.org/keywords/field-programmable-gate-array","display_name":"Field-programmable gate array","score":0.17264172434806824},{"id":"https://openalex.org/keywords/artificial-intelligence","display_name":"Artificial intelligence","score":0.0976298451423645}],"concepts":[{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.7620555758476257},{"id":"https://openalex.org/C7366592","wikidata":"https://www.wikidata.org/wiki/Q1255620","display_name":"Dram","level":2,"score":0.7045110464096069},{"id":"https://openalex.org/C56372850","wikidata":"https://www.wikidata.org/wiki/Q1050404","display_name":"Sparse matrix","level":3,"score":0.5461451411247253},{"id":"https://openalex.org/C153083717","wikidata":"https://www.wikidata.org/wiki/Q6535263","display_name":"Leverage (statistics)","level":2,"score":0.5340911746025085},{"id":"https://openalex.org/C9390403","wikidata":"https://www.wikidata.org/wiki/Q3966","display_name":"Computer hardware","level":1,"score":0.5273854732513428},{"id":"https://openalex.org/C173608175","wikidata":"https://www.wikidata.org/wiki/Q232661","display_name":"Parallel computing","level":1,"score":0.4543125629425049},{"id":"https://openalex.org/C17349429","wikidata":"https://www.wikidata.org/wiki/Q1049914","display_name":"Matrix multiplication","level":3,"score":0.4510372281074524},{"id":"https://openalex.org/C2777904410","wikidata":"https://www.wikidata.org/wiki/Q7397","display_name":"Software","level":2,"score":0.4330577850341797},{"id":"https://openalex.org/C118524514","wikidata":"https://www.wikidata.org/wiki/Q173212","display_name":"Computer architecture","level":1,"score":0.4273565709590912},{"id":"https://openalex.org/C13164978","wikidata":"https://www.wikidata.org/wiki/Q600158","display_name":"Hardware acceleration","level":3,"score":0.4260774254798889},{"id":"https://openalex.org/C188045654","wikidata":"https://www.wikidata.org/wiki/Q17148339","display_name":"Memory bandwidth","level":2,"score":0.41151660680770874},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.3313905894756317},{"id":"https://openalex.org/C42935608","wikidata":"https://www.wikidata.org/wiki/Q190411","display_name":"Field-programmable gate array","level":2,"score":0.17264172434806824},{"id":"https://openalex.org/C154945302","wikidata":"https://www.wikidata.org/wiki/Q11660","display_name":"Artificial intelligence","level":1,"score":0.0976298451423645},{"id":"https://openalex.org/C163716315","wikidata":"https://www.wikidata.org/wiki/Q901177","display_name":"Gaussian","level":2,"score":0.0},{"id":"https://openalex.org/C199360897","wikidata":"https://www.wikidata.org/wiki/Q9143","display_name":"Programming language","level":1,"score":0.0},{"id":"https://openalex.org/C84114770","wikidata":"https://www.wikidata.org/wiki/Q46344","display_name":"Quantum","level":2,"score":0.0},{"id":"https://openalex.org/C121332964","wikidata":"https://www.wikidata.org/wiki/Q413","display_name":"Physics","level":0,"score":0.0},{"id":"https://openalex.org/C62520636","wikidata":"https://www.wikidata.org/wiki/Q944","display_name":"Quantum mechanics","level":1,"score":0.0}],"mesh":[],"locations_count":7,"locations":[{"id":"doi:10.1109/hpec.2013.6670336","is_oa":false,"landing_page_url":"https://doi.org/10.1109/hpec.2013.6670336","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2013 IEEE High Performance Extreme Computing Conference (HPEC)","raw_type":"proceedings-article"},{"id":"pmh:oai:repository.cmu.edu:ece-1252","is_oa":false,"landing_page_url":"http://repository.cmu.edu/ece/260","pdf_url":null,"source":{"id":"https://openalex.org/S4306400668","display_name":"Research Showcase @ Carnegie Mellon University (Carnegie Mellon University)","issn_l":null,"issn":null,"is_oa":false,"is_in_doaj":false,"is_core":false,"host_organization":"https://openalex.org/I74973139","host_organization_name":"Carnegie Mellon University","host_organization_lineage":["https://openalex.org/I74973139"],"host_organization_lineage_names":[],"type":"repository"},"license":null,"license_id":null,"version":"submittedVersion","is_accepted":false,"is_published":false,"raw_source_name":"Department of Electrical and Computer Engineering","raw_type":"text"},{"id":"pmh:doi:10.1184/r1/6468275","is_oa":false,"landing_page_url":null,"pdf_url":null,"source":{"id":"https://openalex.org/S4406922384","display_name":"Open MIND","issn_l":null,"issn":null,"is_oa":false,"is_in_doaj":false,"is_core":false,"host_organization":null,"host_organization_name":null,"host_organization_lineage":[],"host_organization_lineage_names":[],"type":"repository"},"license":null,"license_id":null,"version":"submittedVersion","is_accepted":false,"is_published":false,"raw_source_name":null,"raw_type":"Journal contribution"},{"id":"pmh:oai:CiteSeerX.psu:10.1.1.650.5843","is_oa":false,"landing_page_url":"http://citeseerx.ist.psu.edu/viewdoc/summary?doi=10.1.1.650.5843","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"submittedVersion","is_accepted":false,"is_published":false,"raw_source_name":"http://users.ece.cmu.edu/~franzf/papers/hpec2013.pdf","raw_type":"text"},{"id":"pmh:oai:CiteSeerX.psu:10.1.1.849.5930","is_oa":false,"landing_page_url":"http://citeseerx.ist.psu.edu/viewdoc/summary?doi=10.1.1.849.5930","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"submittedVersion","is_accepted":false,"is_published":false,"raw_source_name":"http://repository.cmu.edu/cgi/viewcontent.cgi?article%3D1252%26context%3Dece","raw_type":"text"},{"id":"pmh:oai:figshare.com:article/6468275","is_oa":true,"landing_page_url":"https://figshare.com/articles/journal_contribution/Accelerating_Sparse_Matrix-Matrix_Multiplication_with_3D-Stacked_Logic-in-Memory_Hardware/6468275","pdf_url":null,"source":{"id":"https://openalex.org/S4377196282","display_name":"Figshare","issn_l":null,"issn":null,"is_oa":false,"is_in_doaj":false,"is_core":false,"host_organization":"https://openalex.org/I4210132348","host_organization_name":"Figshare (United Kingdom)","host_organization_lineage":["https://openalex.org/I4210132348"],"host_organization_lineage_names":[],"type":"repository"},"license":"cc-by","license_id":"https://openalex.org/licenses/cc-by","version":"submittedVersion","is_accepted":false,"is_published":false,"raw_source_name":"","raw_type":"Text"},{"id":"doi:10.1184/r1/6468275.v1","is_oa":true,"landing_page_url":"https://doi.org/10.1184/r1/6468275.v1","pdf_url":null,"source":{"id":"https://openalex.org/S7407050927","display_name":"KiltHub Repository","issn_l":null,"issn":[],"is_oa":false,"is_in_doaj":false,"is_core":false,"host_organization":null,"host_organization_name":null,"host_organization_lineage":[],"host_organization_lineage_names":[],"type":"repository"},"license":null,"license_id":null,"version":null,"is_accepted":false,"is_published":null,"raw_source_name":null,"raw_type":"article-journal"}],"best_oa_location":{"id":"pmh:oai:figshare.com:article/6468275","is_oa":true,"landing_page_url":"https://figshare.com/articles/journal_contribution/Accelerating_Sparse_Matrix-Matrix_Multiplication_with_3D-Stacked_Logic-in-Memory_Hardware/6468275","pdf_url":null,"source":{"id":"https://openalex.org/S4377196282","display_name":"Figshare","issn_l":null,"issn":null,"is_oa":false,"is_in_doaj":false,"is_core":false,"host_organization":"https://openalex.org/I4210132348","host_organization_name":"Figshare (United Kingdom)","host_organization_lineage":["https://openalex.org/I4210132348"],"host_organization_lineage_names":[],"type":"repository"},"license":"cc-by","license_id":"https://openalex.org/licenses/cc-by","version":"submittedVersion","is_accepted":false,"is_published":false,"raw_source_name":"","raw_type":"Text"},"sustainable_development_goals":[{"id":"https://metadata.un.org/sdg/7","display_name":"Affordable and clean energy","score":0.8999999761581421}],"awards":[],"funders":[],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":38,"referenced_works":["https://openalex.org/W26556108","https://openalex.org/W1543862374","https://openalex.org/W1598993252","https://openalex.org/W1761613037","https://openalex.org/W1981550505","https://openalex.org/W1986409410","https://openalex.org/W2013435193","https://openalex.org/W2034062945","https://openalex.org/W2035080386","https://openalex.org/W2062143991","https://openalex.org/W2106612434","https://openalex.org/W2122515712","https://openalex.org/W2122948532","https://openalex.org/W2128680941","https://openalex.org/W2128853364","https://openalex.org/W2130304700","https://openalex.org/W2130328129","https://openalex.org/W2131413854","https://openalex.org/W2134237243","https://openalex.org/W2139730616","https://openalex.org/W2143670137","https://openalex.org/W2150909864","https://openalex.org/W2154235366","https://openalex.org/W2169660606","https://openalex.org/W2170382128","https://openalex.org/W2321154369","https://openalex.org/W3139689176","https://openalex.org/W3146304534","https://openalex.org/W3146763006","https://openalex.org/W4230104114","https://openalex.org/W4247561796","https://openalex.org/W4285719527","https://openalex.org/W6676317001","https://openalex.org/W6676367596","https://openalex.org/W6678879765","https://openalex.org/W6679746154","https://openalex.org/W6682164510","https://openalex.org/W6682819601"],"related_works":["https://openalex.org/W2293771254","https://openalex.org/W4221142455","https://openalex.org/W3121828480","https://openalex.org/W2039875226","https://openalex.org/W2914631005","https://openalex.org/W2032786851","https://openalex.org/W2952630098","https://openalex.org/W3132517792","https://openalex.org/W1541167181","https://openalex.org/W4285148873"],"abstract_inverted_index":{"This":[0],"paper":[1],"introduces":[2],"a":[3,20,26],"3D-stacked":[4],"logic-in-memory":[5],"(LiM)":[6],"system":[7],"to":[8,34,68,83,96],"accelerate":[9],"the":[10,36,43,57,70,78,86,92,98,123],"processing":[11],"of":[12,113,115],"sparse":[13,38,59],"matrix":[14,60],"data":[15,39,81],"that":[16,49],"is":[17],"held":[18],"in":[19,52],"3D":[21],"DRAM":[22,54],"system.":[23],"We":[24],"build":[25],"customized":[27],"content":[28],"addressable":[29],"memory":[30],"(CAM)":[31],"hardware":[32,46,88,104],"structure":[33,82],"exploit":[35],"inherent":[37],"patterns":[40],"and":[41,80,90,102,117],"model":[42],"LiM":[44,103],"based":[45],"accelerator":[47],"layers":[48],"are":[50,66],"stacked":[51],"between":[53],"dies":[55],"for":[56],"efficient":[58],"operations.":[61],"Through":[62],"silicon":[63],"vias":[64],"(TSVs)":[65],"used":[67],"provide":[69],"required":[71],"high":[72],"inter-layer":[73],"bandwidth.":[74],"Furthermore,":[75],"we":[76],"adapt":[77],"algorithm":[79],"fully":[84],"leverage":[85],"underlying":[87],"capabilities,":[89],"develop":[91],"necessary":[93],"design":[94,99],"framework":[95],"facilitate":[97],"space":[100],"evaluation":[101],"synthesis.":[105],"Our":[106],"simulation":[107],"demonstrates":[108],"more":[109],"than":[110],"two":[111],"orders":[112],"magnitude":[114],"performance":[116],"energy":[118],"efficiency":[119],"improvements":[120],"compared":[121],"with":[122],"traditional":[124],"multithreaded":[125],"software":[126],"implementation":[127],"on":[128],"modern":[129],"processors.":[130]},"counts_by_year":[{"year":2025,"cited_by_count":7},{"year":2024,"cited_by_count":4},{"year":2023,"cited_by_count":6},{"year":2022,"cited_by_count":12},{"year":2021,"cited_by_count":15},{"year":2020,"cited_by_count":7},{"year":2019,"cited_by_count":13},{"year":2018,"cited_by_count":16},{"year":2017,"cited_by_count":11},{"year":2016,"cited_by_count":7},{"year":2015,"cited_by_count":9},{"year":2014,"cited_by_count":2},{"year":2013,"cited_by_count":1}],"updated_date":"2026-04-05T17:49:38.594831","created_date":"2025-10-10T00:00:00"}