{"id":"https://openalex.org/W2555742548","doi":"https://doi.org/10.1109/hldvt.2016.7748248","title":"Synthesizable SVA protocol checker generation methodology based on TDML and VCD file formats","display_name":"Synthesizable SVA protocol checker generation methodology based on TDML and VCD file formats","publication_year":2016,"publication_date":"2016-10-01","ids":{"openalex":"https://openalex.org/W2555742548","doi":"https://doi.org/10.1109/hldvt.2016.7748248","mag":"2555742548"},"language":"en","primary_location":{"id":"doi:10.1109/hldvt.2016.7748248","is_oa":false,"landing_page_url":"https://doi.org/10.1109/hldvt.2016.7748248","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2016 IEEE International High Level Design Validation and Test Workshop (HLDVT)","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5005930482","display_name":"Mohamed O. Kayed","orcid":null},"institutions":[],"countries":[],"is_corresponding":true,"raw_author_name":"Mohamed O. Kayed","raw_affiliation_strings":["Mentor Graphics, Cairo, Egypt"],"affiliations":[{"raw_affiliation_string":"Mentor Graphics, Cairo, Egypt","institution_ids":[]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5101764720","display_name":"Mohamed AbdelSalam","orcid":"https://orcid.org/0000-0002-1409-199X"},"institutions":[],"countries":[],"is_corresponding":false,"raw_author_name":"Mohamed Abdelsalam","raw_affiliation_strings":["Mentor Graphics, Cairo, Egypt"],"affiliations":[{"raw_affiliation_string":"Mentor Graphics, Cairo, Egypt","institution_ids":[]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5009910243","display_name":"Rafik Guindi","orcid":null},"institutions":[{"id":"https://openalex.org/I57629906","display_name":"Nile University","ror":"https://ror.org/03cg7cp61","country_code":"EG","type":"education","lineage":["https://openalex.org/I57629906"]}],"countries":["EG"],"is_corresponding":false,"raw_author_name":"Rafik Guindi","raw_affiliation_strings":["Nile University, Cairo, Egypt"],"affiliations":[{"raw_affiliation_string":"Nile University, Cairo, Egypt","institution_ids":["https://openalex.org/I57629906"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":3,"corresponding_author_ids":["https://openalex.org/A5005930482"],"corresponding_institution_ids":[],"apc_list":null,"apc_paid":null,"fwci":0.3485,"has_fulltext":false,"cited_by_count":2,"citation_normalized_percentile":{"value":0.68895528,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":90,"max":95},"biblio":{"volume":null,"issue":null,"first_page":"1","last_page":"8"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10142","display_name":"Formal Methods in Verification","score":0.9998000264167786,"subfield":{"id":"https://openalex.org/subfields/1703","display_name":"Computational Theory and Mathematics"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10142","display_name":"Formal Methods in Verification","score":0.9998000264167786,"subfield":{"id":"https://openalex.org/subfields/1703","display_name":"Computational Theory and Mathematics"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11005","display_name":"Radiation Effects in Electronics","score":0.9993000030517578,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11032","display_name":"VLSI and Analog Circuit Testing","score":0.9991999864578247,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.7744871377944946},{"id":"https://openalex.org/keywords/verilog","display_name":"Verilog","score":0.6840610504150391},{"id":"https://openalex.org/keywords/emulation","display_name":"Emulation","score":0.6296771764755249},{"id":"https://openalex.org/keywords/protocol","display_name":"Protocol (science)","score":0.6154215335845947},{"id":"https://openalex.org/keywords/hardware-emulation","display_name":"Hardware emulation","score":0.5338723659515381},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.47060853242874146},{"id":"https://openalex.org/keywords/computer-architecture","display_name":"Computer architecture","score":0.44590887427330017},{"id":"https://openalex.org/keywords/model-checking","display_name":"Model checking","score":0.41965028643608093},{"id":"https://openalex.org/keywords/verification","display_name":"Verification","score":0.41549813747406006},{"id":"https://openalex.org/keywords/programming-language","display_name":"Programming language","score":0.37041956186294556},{"id":"https://openalex.org/keywords/software-engineering","display_name":"Software engineering","score":0.3522477149963379},{"id":"https://openalex.org/keywords/field-programmable-gate-array","display_name":"Field-programmable gate array","score":0.22553086280822754},{"id":"https://openalex.org/keywords/software","display_name":"Software","score":0.17235395312309265}],"concepts":[{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.7744871377944946},{"id":"https://openalex.org/C2779030575","wikidata":"https://www.wikidata.org/wiki/Q827773","display_name":"Verilog","level":3,"score":0.6840610504150391},{"id":"https://openalex.org/C149810388","wikidata":"https://www.wikidata.org/wiki/Q5374873","display_name":"Emulation","level":2,"score":0.6296771764755249},{"id":"https://openalex.org/C2780385302","wikidata":"https://www.wikidata.org/wiki/Q367158","display_name":"Protocol (science)","level":3,"score":0.6154215335845947},{"id":"https://openalex.org/C94115699","wikidata":"https://www.wikidata.org/wiki/Q5656406","display_name":"Hardware emulation","level":3,"score":0.5338723659515381},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.47060853242874146},{"id":"https://openalex.org/C118524514","wikidata":"https://www.wikidata.org/wiki/Q173212","display_name":"Computer architecture","level":1,"score":0.44590887427330017},{"id":"https://openalex.org/C110251889","wikidata":"https://www.wikidata.org/wiki/Q1569697","display_name":"Model checking","level":2,"score":0.41965028643608093},{"id":"https://openalex.org/C142284323","wikidata":"https://www.wikidata.org/wiki/Q7921323","display_name":"Verification","level":5,"score":0.41549813747406006},{"id":"https://openalex.org/C199360897","wikidata":"https://www.wikidata.org/wiki/Q9143","display_name":"Programming language","level":1,"score":0.37041956186294556},{"id":"https://openalex.org/C115903868","wikidata":"https://www.wikidata.org/wiki/Q80993","display_name":"Software engineering","level":1,"score":0.3522477149963379},{"id":"https://openalex.org/C42935608","wikidata":"https://www.wikidata.org/wiki/Q190411","display_name":"Field-programmable gate array","level":2,"score":0.22553086280822754},{"id":"https://openalex.org/C2777904410","wikidata":"https://www.wikidata.org/wiki/Q7397","display_name":"Software","level":2,"score":0.17235395312309265},{"id":"https://openalex.org/C162324750","wikidata":"https://www.wikidata.org/wiki/Q8134","display_name":"Economics","level":0,"score":0.0},{"id":"https://openalex.org/C186846655","wikidata":"https://www.wikidata.org/wiki/Q3398377","display_name":"Software construction","level":4,"score":0.0},{"id":"https://openalex.org/C142724271","wikidata":"https://www.wikidata.org/wiki/Q7208","display_name":"Pathology","level":1,"score":0.0},{"id":"https://openalex.org/C149091818","wikidata":"https://www.wikidata.org/wiki/Q2429814","display_name":"Software system","level":3,"score":0.0},{"id":"https://openalex.org/C50522688","wikidata":"https://www.wikidata.org/wiki/Q189833","display_name":"Economic growth","level":1,"score":0.0},{"id":"https://openalex.org/C71924100","wikidata":"https://www.wikidata.org/wiki/Q11190","display_name":"Medicine","level":0,"score":0.0},{"id":"https://openalex.org/C204787440","wikidata":"https://www.wikidata.org/wiki/Q188504","display_name":"Alternative medicine","level":2,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/hldvt.2016.7748248","is_oa":false,"landing_page_url":"https://doi.org/10.1109/hldvt.2016.7748248","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2016 IEEE International High Level Design Validation and Test Workshop (HLDVT)","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[{"score":0.4099999964237213,"id":"https://metadata.un.org/sdg/9","display_name":"Industry, innovation and infrastructure"}],"awards":[],"funders":[],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":6,"referenced_works":["https://openalex.org/W2047390668","https://openalex.org/W2117009616","https://openalex.org/W2152864604","https://openalex.org/W2168238416","https://openalex.org/W3142765463","https://openalex.org/W6662309529"],"related_works":["https://openalex.org/W2170071008","https://openalex.org/W2103996454","https://openalex.org/W2106791114","https://openalex.org/W3029775214","https://openalex.org/W2390650884","https://openalex.org/W2093057572","https://openalex.org/W2129151116","https://openalex.org/W2001552871","https://openalex.org/W1974143443","https://openalex.org/W2353557016"],"abstract_inverted_index":{"System":[0],"Verilog":[1],"Assertions":[2],"(SVA)":[3],"is":[4],"widely":[5],"used":[6,65],"by":[7],"hardware":[8,22,95,114],"designers":[9,45,96],"and":[10,34,46,97,119],"verification":[11,47,98],"engineers":[12,48,99],"to":[13,58,66,100,105],"apply":[14],"Assertion":[15],"Based":[16],"Verification":[17],"(ABV)":[18],"methodology":[19],"on":[20,44,113],"their":[21,110],"designs.":[23],"However,":[24],"the":[25,85,102,107,120],"complexity":[26],"in":[27,32,39],"understanding":[28],"different":[29],"protocol":[30,37],"standards":[31,38],"general":[33],"JEDEC":[35,82,133],"memory":[36,72],"specific":[40],"imposes":[41],"numerous":[42],"difficulties":[43],"when":[49,77],"translating":[50],"design":[51,79,111],"specifications":[52],"into":[53],"SVA.":[54],"This":[55],"motivated":[56],"us":[57],"devise":[59],"new":[60],"techniques":[61],"that":[62],"can":[63],"be":[64],"automatically":[67],"generate":[68,90],"SVA":[69],"for":[70],"DDR":[71],"protocols":[73],"with":[74,127],"no":[75],"ambiguity":[76],"capturing":[78],"requirements":[80],"from":[81],"standards.":[83],"Moreover,":[84],"proposed":[86],"assertions":[87,104],"generation":[88],"methods":[89],"\"synthesizable":[91],"SVA\",":[92],"hence":[93],"allowing":[94],"use":[101],"generated":[103],"check":[106],"functionality":[108],"of":[109,122],"implementation":[112],"emulation":[115],"platforms.":[116],"The":[117],"viability":[118],"potential":[121],"our":[123],"work":[124],"are":[125],"demonstrated":[126],"an":[128],"Industrial":[129],"case":[130],"study":[131],"using":[132],"LPDDR3":[134],"Memory":[135],"Protocol":[136],"Standard.":[137]},"counts_by_year":[{"year":2025,"cited_by_count":1},{"year":2018,"cited_by_count":1}],"updated_date":"2025-11-06T03:46:38.306776","created_date":"2025-10-10T00:00:00"}