{"id":"https://openalex.org/W2155555096","doi":"https://doi.org/10.1109/hicss.1994.323176","title":"Performance of the RamLink memory architecture","display_name":"Performance of the RamLink memory architecture","publication_year":1994,"publication_date":"1994-01-01","ids":{"openalex":"https://openalex.org/W2155555096","doi":"https://doi.org/10.1109/hicss.1994.323176","mag":"2155555096"},"language":"en","primary_location":{"id":"doi:10.1109/hicss.1994.323176","is_oa":false,"landing_page_url":"https://doi.org/10.1109/hicss.1994.323176","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Proceedings of the Twenty-Seventh Hawaii International Conference on System Sciences HICSS-94","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5032108766","display_name":"Stein Gjessing","orcid":null},"institutions":[{"id":"https://openalex.org/I184942183","display_name":"University of Oslo","ror":"https://ror.org/01xtthb56","country_code":"NO","type":"education","lineage":["https://openalex.org/I184942183"]}],"countries":["NO"],"is_corresponding":true,"raw_author_name":"S. Gjessing","raw_affiliation_strings":["University of Oslo, Oslo, Norway"],"affiliations":[{"raw_affiliation_string":"University of Oslo, Oslo, Norway","institution_ids":["https://openalex.org/I184942183"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5082976429","display_name":"G. Stone","orcid":null},"institutions":[{"id":"https://openalex.org/I4210153776","display_name":"Apple (United States)","ror":"https://ror.org/059hsda18","country_code":"US","type":"company","lineage":["https://openalex.org/I4210153776"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"G. Stone","raw_affiliation_strings":["Apple Computer, Inc., Cupertino, CA, USA"],"affiliations":[{"raw_affiliation_string":"Apple Computer, Inc., Cupertino, CA, USA","institution_ids":["https://openalex.org/I4210153776"]}]}],"institutions":[],"countries_distinct_count":2,"institutions_distinct_count":2,"corresponding_author_ids":["https://openalex.org/A5032108766"],"corresponding_institution_ids":["https://openalex.org/I184942183"],"apc_list":null,"apc_paid":null,"fwci":0.3975,"has_fulltext":false,"cited_by_count":1,"citation_normalized_percentile":{"value":0.68858909,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":null,"biblio":{"volume":null,"issue":null,"first_page":"154","last_page":"162"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10054","display_name":"Parallel Computing and Optimization Techniques","score":1.0,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10054","display_name":"Parallel Computing and Optimization Techniques","score":1.0,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11181","display_name":"Advanced Data Storage Technologies","score":0.9998000264167786,"subfield":{"id":"https://openalex.org/subfields/1705","display_name":"Computer Networks and Communications"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10829","display_name":"Interconnection Networks and Systems","score":0.9995999932289124,"subfield":{"id":"https://openalex.org/subfields/1705","display_name":"Computer Networks and Communications"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.7915925979614258},{"id":"https://openalex.org/keywords/memory-controller","display_name":"Memory controller","score":0.7865409851074219},{"id":"https://openalex.org/keywords/architecture","display_name":"Architecture","score":0.549194872379303},{"id":"https://openalex.org/keywords/memory-map","display_name":"Memory map","score":0.531055212020874},{"id":"https://openalex.org/keywords/memory-refresh","display_name":"Memory refresh","score":0.4958387315273285},{"id":"https://openalex.org/keywords/controller","display_name":"Controller (irrigation)","score":0.4942755699157715},{"id":"https://openalex.org/keywords/bandwidth","display_name":"Bandwidth (computing)","score":0.48208314180374146},{"id":"https://openalex.org/keywords/protocol","display_name":"Protocol (science)","score":0.48108407855033875},{"id":"https://openalex.org/keywords/registered-memory","display_name":"Registered memory","score":0.45163968205451965},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.44871100783348083},{"id":"https://openalex.org/keywords/memory-architecture","display_name":"Memory architecture","score":0.43791621923446655},{"id":"https://openalex.org/keywords/semiconductor-memory","display_name":"Semiconductor memory","score":0.4328475296497345},{"id":"https://openalex.org/keywords/interleaved-memory","display_name":"Interleaved memory","score":0.41705724596977234},{"id":"https://openalex.org/keywords/memory-bandwidth","display_name":"Memory bandwidth","score":0.4148833453655243},{"id":"https://openalex.org/keywords/memory-management","display_name":"Memory management","score":0.37640419602394104},{"id":"https://openalex.org/keywords/computer-architecture","display_name":"Computer architecture","score":0.3659825325012207},{"id":"https://openalex.org/keywords/computer-hardware","display_name":"Computer hardware","score":0.3262253403663635},{"id":"https://openalex.org/keywords/computer-memory","display_name":"Computer memory","score":0.31548959016799927},{"id":"https://openalex.org/keywords/computer-network","display_name":"Computer network","score":0.21160337328910828}],"concepts":[{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.7915925979614258},{"id":"https://openalex.org/C100800780","wikidata":"https://www.wikidata.org/wiki/Q1175867","display_name":"Memory controller","level":3,"score":0.7865409851074219},{"id":"https://openalex.org/C123657996","wikidata":"https://www.wikidata.org/wiki/Q12271","display_name":"Architecture","level":2,"score":0.549194872379303},{"id":"https://openalex.org/C74426580","wikidata":"https://www.wikidata.org/wiki/Q719484","display_name":"Memory map","level":3,"score":0.531055212020874},{"id":"https://openalex.org/C87907426","wikidata":"https://www.wikidata.org/wiki/Q6815755","display_name":"Memory refresh","level":4,"score":0.4958387315273285},{"id":"https://openalex.org/C203479927","wikidata":"https://www.wikidata.org/wiki/Q5165939","display_name":"Controller (irrigation)","level":2,"score":0.4942755699157715},{"id":"https://openalex.org/C2776257435","wikidata":"https://www.wikidata.org/wiki/Q1576430","display_name":"Bandwidth (computing)","level":2,"score":0.48208314180374146},{"id":"https://openalex.org/C2780385302","wikidata":"https://www.wikidata.org/wiki/Q367158","display_name":"Protocol (science)","level":3,"score":0.48108407855033875},{"id":"https://openalex.org/C93446704","wikidata":"https://www.wikidata.org/wiki/Q449328","display_name":"Registered memory","level":3,"score":0.45163968205451965},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.44871100783348083},{"id":"https://openalex.org/C2779602883","wikidata":"https://www.wikidata.org/wiki/Q15544750","display_name":"Memory architecture","level":2,"score":0.43791621923446655},{"id":"https://openalex.org/C98986596","wikidata":"https://www.wikidata.org/wiki/Q1143031","display_name":"Semiconductor memory","level":2,"score":0.4328475296497345},{"id":"https://openalex.org/C63511323","wikidata":"https://www.wikidata.org/wiki/Q908936","display_name":"Interleaved memory","level":4,"score":0.41705724596977234},{"id":"https://openalex.org/C188045654","wikidata":"https://www.wikidata.org/wiki/Q17148339","display_name":"Memory bandwidth","level":2,"score":0.4148833453655243},{"id":"https://openalex.org/C176649486","wikidata":"https://www.wikidata.org/wiki/Q2308807","display_name":"Memory management","level":3,"score":0.37640419602394104},{"id":"https://openalex.org/C118524514","wikidata":"https://www.wikidata.org/wiki/Q173212","display_name":"Computer architecture","level":1,"score":0.3659825325012207},{"id":"https://openalex.org/C9390403","wikidata":"https://www.wikidata.org/wiki/Q3966","display_name":"Computer hardware","level":1,"score":0.3262253403663635},{"id":"https://openalex.org/C92855701","wikidata":"https://www.wikidata.org/wiki/Q5830907","display_name":"Computer memory","level":3,"score":0.31548959016799927},{"id":"https://openalex.org/C31258907","wikidata":"https://www.wikidata.org/wiki/Q1301371","display_name":"Computer network","level":1,"score":0.21160337328910828},{"id":"https://openalex.org/C6557445","wikidata":"https://www.wikidata.org/wiki/Q173113","display_name":"Agronomy","level":1,"score":0.0},{"id":"https://openalex.org/C142724271","wikidata":"https://www.wikidata.org/wiki/Q7208","display_name":"Pathology","level":1,"score":0.0},{"id":"https://openalex.org/C142362112","wikidata":"https://www.wikidata.org/wiki/Q735","display_name":"Art","level":0,"score":0.0},{"id":"https://openalex.org/C153349607","wikidata":"https://www.wikidata.org/wiki/Q36649","display_name":"Visual arts","level":1,"score":0.0},{"id":"https://openalex.org/C71924100","wikidata":"https://www.wikidata.org/wiki/Q11190","display_name":"Medicine","level":0,"score":0.0},{"id":"https://openalex.org/C86803240","wikidata":"https://www.wikidata.org/wiki/Q420","display_name":"Biology","level":0,"score":0.0},{"id":"https://openalex.org/C204787440","wikidata":"https://www.wikidata.org/wiki/Q188504","display_name":"Alternative medicine","level":2,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/hicss.1994.323176","is_oa":false,"landing_page_url":"https://doi.org/10.1109/hicss.1994.323176","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Proceedings of the Twenty-Seventh Hawaii International Conference on System Sciences HICSS-94","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[],"awards":[],"funders":[{"id":"https://openalex.org/F4320323299","display_name":"Norges Forskningsr\u00e5d","ror":"https://ror.org/00epmv149"}],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":9,"referenced_works":["https://openalex.org/W1589527529","https://openalex.org/W2001056873","https://openalex.org/W2002554499","https://openalex.org/W2037540668","https://openalex.org/W2115043123","https://openalex.org/W2157381427","https://openalex.org/W2159117078","https://openalex.org/W2798981073","https://openalex.org/W3021483259"],"related_works":["https://openalex.org/W4285141256","https://openalex.org/W3029446734","https://openalex.org/W4243618206","https://openalex.org/W1986822391","https://openalex.org/W2155373950","https://openalex.org/W2138825797","https://openalex.org/W2051602492","https://openalex.org/W2114859707","https://openalex.org/W3093911585","https://openalex.org/W2044064773"],"abstract_inverted_index":{"RamLink":[0,18,55,72,131,138,155,167],"is":[1,43,50,124],"a":[2,12,23,27,34,59,92,102,169,175],"proposal":[3],"by":[4,159],"the":[5,41,47,68,98,106,127,137,151,154,160],"P1596.4":[6],"IEEE":[7,161],"working":[8,162],"group":[9],"for":[10],"defining":[11],"high":[13,170],"bandwidth":[14,171],"memory":[15,19,24,30,56,69,86,99,103,115,172],"architecture.":[16],"A":[17],"system":[20,173],"consists":[21],"of":[22,29,40,84,96,121,130,153],"controller":[25,57],"and":[26,46,101,132],"number":[28],"chips":[31,100],"connected":[32],"in":[33,136],"ring":[35,42],"topology.":[36],"The":[37,54,71,119,140],"signaling":[38],"rate":[39],"two":[44],"nanoseconds":[45],"data":[48],"lane":[49],"eight":[51],"bits":[52],"wide.":[53],"implements":[58],"packet":[60],"based":[61],"protocol":[62,73,111],"to":[63,67,125,133,143,168],"issue":[64],"read/write":[65,116],"requests":[66],"chips.":[70],"supports":[74],"concurrent":[75],"transfers,":[76],"making":[77],"performance":[78,129,149],"prediction":[79],"more":[80],"difficult":[81],"than":[82],"that":[83,145],"typical":[85],"interfaces.":[87],"Therefore,":[88],"we":[89,108],"have":[90],"built":[91],"detailed":[93],"simulation":[94],"model":[95],"both":[97],"controller.":[104],"Using":[105],"simulator":[107],"can":[109],"observe":[110],"behavior":[112],"under":[113],"various":[114],"access":[117],"scenarios.":[118],"focus":[120],"our":[122],"research":[123],"verify":[126],"expected":[128],"identify":[134],"limitations":[135],"protocol.":[139],"authors":[141],"wish":[142],"emphasize":[144],"this":[146],"paper":[147],"presents":[148],"simulations:":[150],"details":[152],"architecture":[156],"are":[157],"specified":[158],"group.":[163],"We":[164],"also":[165],"compare":[166],"using":[174],"buslike":[176],"architecture.<":[177],"<ETX":[178],"xmlns:mml=\"http://www.w3.org/1998/Math/MathML\"":[179],"xmlns:xlink=\"http://www.w3.org/1999/xlink\">&gt;</ETX>":[180]},"counts_by_year":[],"updated_date":"2025-11-06T03:46:38.306776","created_date":"2025-10-10T00:00:00"}