{"id":"https://openalex.org/W2136272868","doi":"https://doi.org/10.1109/hicss.1994.323142","title":"Experimental implementation of dynamic access ordering","display_name":"Experimental implementation of dynamic access ordering","publication_year":1994,"publication_date":"1994-01-01","ids":{"openalex":"https://openalex.org/W2136272868","doi":"https://doi.org/10.1109/hicss.1994.323142","mag":"2136272868"},"language":"en","primary_location":{"id":"doi:10.1109/hicss.1994.323142","is_oa":false,"landing_page_url":"https://doi.org/10.1109/hicss.1994.323142","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Proceedings of the Twenty-Seventh Hawaii International Conference on System Sciences HICSS-94","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5022715353","display_name":"Sally A. McKee","orcid":"https://orcid.org/0000-0003-0514-3767"},"institutions":[{"id":"https://openalex.org/I51556381","display_name":"University of Virginia","ror":"https://ror.org/0153tk833","country_code":"US","type":"education","lineage":["https://openalex.org/I51556381"]}],"countries":["US"],"is_corresponding":true,"raw_author_name":"S.A. McKee","raw_affiliation_strings":["University of Virginia, France","[Virginia Univ., Charlottesville, VA, USA]"],"affiliations":[{"raw_affiliation_string":"University of Virginia, France","institution_ids":["https://openalex.org/I51556381"]},{"raw_affiliation_string":"[Virginia Univ., Charlottesville, VA, USA]","institution_ids":["https://openalex.org/I51556381"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5103729911","display_name":"Robert H. Klenke","orcid":null},"institutions":[{"id":"https://openalex.org/I51556381","display_name":"University of Virginia","ror":"https://ror.org/0153tk833","country_code":"US","type":"education","lineage":["https://openalex.org/I51556381"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"R.H. Klenke","raw_affiliation_strings":["University of Virginia, France","[Virginia Univ., Charlottesville, VA, USA]"],"affiliations":[{"raw_affiliation_string":"University of Virginia, France","institution_ids":["https://openalex.org/I51556381"]},{"raw_affiliation_string":"[Virginia Univ., Charlottesville, VA, USA]","institution_ids":["https://openalex.org/I51556381"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5060074592","display_name":"Andrew J. Schwab","orcid":"https://orcid.org/0000-0002-1517-4308"},"institutions":[{"id":"https://openalex.org/I51556381","display_name":"University of Virginia","ror":"https://ror.org/0153tk833","country_code":"US","type":"education","lineage":["https://openalex.org/I51556381"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"A.J. Schwab","raw_affiliation_strings":["University of Virginia, France","[Virginia Univ., Charlottesville, VA, USA]"],"affiliations":[{"raw_affiliation_string":"University of Virginia, France","institution_ids":["https://openalex.org/I51556381"]},{"raw_affiliation_string":"[Virginia Univ., Charlottesville, VA, USA]","institution_ids":["https://openalex.org/I51556381"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5111889680","display_name":"Wm. A. Wulf","orcid":null},"institutions":[{"id":"https://openalex.org/I51556381","display_name":"University of Virginia","ror":"https://ror.org/0153tk833","country_code":"US","type":"education","lineage":["https://openalex.org/I51556381"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"W.A. Wulf","raw_affiliation_strings":["University of Virginia, France","[Virginia Univ., Charlottesville, VA, USA]"],"affiliations":[{"raw_affiliation_string":"University of Virginia, France","institution_ids":["https://openalex.org/I51556381"]},{"raw_affiliation_string":"[Virginia Univ., Charlottesville, VA, USA]","institution_ids":["https://openalex.org/I51556381"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5036277849","display_name":"Steven A. Moyer","orcid":null},"institutions":[{"id":"https://openalex.org/I51556381","display_name":"University of Virginia","ror":"https://ror.org/0153tk833","country_code":"US","type":"education","lineage":["https://openalex.org/I51556381"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"S.A. Moyer","raw_affiliation_strings":["University of Virginia, France","[Virginia Univ., Charlottesville, VA, USA]"],"affiliations":[{"raw_affiliation_string":"University of Virginia, France","institution_ids":["https://openalex.org/I51556381"]},{"raw_affiliation_string":"[Virginia Univ., Charlottesville, VA, USA]","institution_ids":["https://openalex.org/I51556381"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5044171543","display_name":"J.H. Aylor","orcid":null},"institutions":[{"id":"https://openalex.org/I51556381","display_name":"University of Virginia","ror":"https://ror.org/0153tk833","country_code":"US","type":"education","lineage":["https://openalex.org/I51556381"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"J.H. Aylor","raw_affiliation_strings":["University of Virginia, France","[Virginia Univ., Charlottesville, VA, USA]"],"affiliations":[{"raw_affiliation_string":"University of Virginia, France","institution_ids":["https://openalex.org/I51556381"]},{"raw_affiliation_string":"[Virginia Univ., Charlottesville, VA, USA]","institution_ids":["https://openalex.org/I51556381"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5041023436","display_name":"Charles Y. Hitchcock","orcid":null},"institutions":[],"countries":[],"is_corresponding":false,"raw_author_name":"C.Y. Hitchcock","raw_affiliation_strings":[],"affiliations":[]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":7,"corresponding_author_ids":["https://openalex.org/A5022715353"],"corresponding_institution_ids":["https://openalex.org/I51556381"],"apc_list":null,"apc_paid":null,"fwci":3.5777,"has_fulltext":false,"cited_by_count":20,"citation_normalized_percentile":{"value":0.92804947,"is_in_top_1_percent":false,"is_in_top_10_percent":true},"cited_by_percentile_year":null,"biblio":{"volume":"29","issue":null,"first_page":"431","last_page":"440"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10054","display_name":"Parallel Computing and Optimization Techniques","score":1.0,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10054","display_name":"Parallel Computing and Optimization Techniques","score":1.0,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11181","display_name":"Advanced Data Storage Technologies","score":0.9998000264167786,"subfield":{"id":"https://openalex.org/subfields/1705","display_name":"Computer Networks and Communications"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10772","display_name":"Distributed systems and fault tolerance","score":0.9987999796867371,"subfield":{"id":"https://openalex.org/subfields/1705","display_name":"Computer Networks and Communications"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.8342123031616211},{"id":"https://openalex.org/keywords/registered-memory","display_name":"Registered memory","score":0.6696678400039673},{"id":"https://openalex.org/keywords/interleaved-memory","display_name":"Interleaved memory","score":0.6575710773468018},{"id":"https://openalex.org/keywords/uniform-memory-access","display_name":"Uniform memory access","score":0.6373356580734253},{"id":"https://openalex.org/keywords/bottleneck","display_name":"Bottleneck","score":0.6172274351119995},{"id":"https://openalex.org/keywords/memory-map","display_name":"Memory map","score":0.6049510836601257},{"id":"https://openalex.org/keywords/memory-bandwidth","display_name":"Memory bandwidth","score":0.5618818998336792},{"id":"https://openalex.org/keywords/memory-controller","display_name":"Memory controller","score":0.5550143718719482},{"id":"https://openalex.org/keywords/flat-memory-model","display_name":"Flat memory model","score":0.5261318683624268},{"id":"https://openalex.org/keywords/dram","display_name":"Dram","score":0.5024442672729492},{"id":"https://openalex.org/keywords/bandwidth","display_name":"Bandwidth (computing)","score":0.5014693737030029},{"id":"https://openalex.org/keywords/dynamic-random-access-memory","display_name":"Dynamic random-access memory","score":0.4972107708454132},{"id":"https://openalex.org/keywords/access-time","display_name":"Access time","score":0.4932071566581726},{"id":"https://openalex.org/keywords/microprocessor","display_name":"Microprocessor","score":0.4874875545501709},{"id":"https://openalex.org/keywords/cas-latency","display_name":"CAS latency","score":0.44001734256744385},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.4219588339328766},{"id":"https://openalex.org/keywords/memory-management","display_name":"Memory management","score":0.35408249497413635},{"id":"https://openalex.org/keywords/parallel-computing","display_name":"Parallel computing","score":0.3442772328853607},{"id":"https://openalex.org/keywords/overlay","display_name":"Overlay","score":0.3416052460670471},{"id":"https://openalex.org/keywords/shared-memory","display_name":"Shared memory","score":0.3253183364868164},{"id":"https://openalex.org/keywords/computer-hardware","display_name":"Computer hardware","score":0.31349265575408936},{"id":"https://openalex.org/keywords/semiconductor-memory","display_name":"Semiconductor memory","score":0.2893817126750946},{"id":"https://openalex.org/keywords/operating-system","display_name":"Operating system","score":0.28423401713371277},{"id":"https://openalex.org/keywords/computer-network","display_name":"Computer network","score":0.15869799256324768}],"concepts":[{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.8342123031616211},{"id":"https://openalex.org/C93446704","wikidata":"https://www.wikidata.org/wiki/Q449328","display_name":"Registered memory","level":3,"score":0.6696678400039673},{"id":"https://openalex.org/C63511323","wikidata":"https://www.wikidata.org/wiki/Q908936","display_name":"Interleaved memory","level":4,"score":0.6575710773468018},{"id":"https://openalex.org/C51290061","wikidata":"https://www.wikidata.org/wiki/Q1936765","display_name":"Uniform memory access","level":4,"score":0.6373356580734253},{"id":"https://openalex.org/C2780513914","wikidata":"https://www.wikidata.org/wiki/Q18210350","display_name":"Bottleneck","level":2,"score":0.6172274351119995},{"id":"https://openalex.org/C74426580","wikidata":"https://www.wikidata.org/wiki/Q719484","display_name":"Memory map","level":3,"score":0.6049510836601257},{"id":"https://openalex.org/C188045654","wikidata":"https://www.wikidata.org/wiki/Q17148339","display_name":"Memory bandwidth","level":2,"score":0.5618818998336792},{"id":"https://openalex.org/C100800780","wikidata":"https://www.wikidata.org/wiki/Q1175867","display_name":"Memory controller","level":3,"score":0.5550143718719482},{"id":"https://openalex.org/C57863822","wikidata":"https://www.wikidata.org/wiki/Q905488","display_name":"Flat memory model","level":4,"score":0.5261318683624268},{"id":"https://openalex.org/C7366592","wikidata":"https://www.wikidata.org/wiki/Q1255620","display_name":"Dram","level":2,"score":0.5024442672729492},{"id":"https://openalex.org/C2776257435","wikidata":"https://www.wikidata.org/wiki/Q1576430","display_name":"Bandwidth (computing)","level":2,"score":0.5014693737030029},{"id":"https://openalex.org/C118702147","wikidata":"https://www.wikidata.org/wiki/Q189396","display_name":"Dynamic random-access memory","level":3,"score":0.4972107708454132},{"id":"https://openalex.org/C194080101","wikidata":"https://www.wikidata.org/wiki/Q46306","display_name":"Access time","level":2,"score":0.4932071566581726},{"id":"https://openalex.org/C2780728072","wikidata":"https://www.wikidata.org/wiki/Q5297","display_name":"Microprocessor","level":2,"score":0.4874875545501709},{"id":"https://openalex.org/C189930140","wikidata":"https://www.wikidata.org/wiki/Q1112878","display_name":"CAS latency","level":4,"score":0.44001734256744385},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.4219588339328766},{"id":"https://openalex.org/C176649486","wikidata":"https://www.wikidata.org/wiki/Q2308807","display_name":"Memory management","level":3,"score":0.35408249497413635},{"id":"https://openalex.org/C173608175","wikidata":"https://www.wikidata.org/wiki/Q232661","display_name":"Parallel computing","level":1,"score":0.3442772328853607},{"id":"https://openalex.org/C136085584","wikidata":"https://www.wikidata.org/wiki/Q910289","display_name":"Overlay","level":2,"score":0.3416052460670471},{"id":"https://openalex.org/C133875982","wikidata":"https://www.wikidata.org/wiki/Q764810","display_name":"Shared memory","level":2,"score":0.3253183364868164},{"id":"https://openalex.org/C9390403","wikidata":"https://www.wikidata.org/wiki/Q3966","display_name":"Computer hardware","level":1,"score":0.31349265575408936},{"id":"https://openalex.org/C98986596","wikidata":"https://www.wikidata.org/wiki/Q1143031","display_name":"Semiconductor memory","level":2,"score":0.2893817126750946},{"id":"https://openalex.org/C111919701","wikidata":"https://www.wikidata.org/wiki/Q9135","display_name":"Operating system","level":1,"score":0.28423401713371277},{"id":"https://openalex.org/C31258907","wikidata":"https://www.wikidata.org/wiki/Q1301371","display_name":"Computer network","level":1,"score":0.15869799256324768}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/hicss.1994.323142","is_oa":false,"landing_page_url":"https://doi.org/10.1109/hicss.1994.323142","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Proceedings of the Twenty-Seventh Hawaii International Conference on System Sciences HICSS-94","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[],"awards":[],"funders":[{"id":"https://openalex.org/F4320306076","display_name":"National Science Foundation","ror":"https://ror.org/021nxhr62"}],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":36,"referenced_works":["https://openalex.org/W604230713","https://openalex.org/W1481890431","https://openalex.org/W1536051636","https://openalex.org/W1584774780","https://openalex.org/W1586616317","https://openalex.org/W1601143231","https://openalex.org/W1976536876","https://openalex.org/W1988425770","https://openalex.org/W1999339108","https://openalex.org/W2010634113","https://openalex.org/W2032843491","https://openalex.org/W2061630631","https://openalex.org/W2098220211","https://openalex.org/W2101735776","https://openalex.org/W2102604868","https://openalex.org/W2105605502","https://openalex.org/W2105823594","https://openalex.org/W2106547797","https://openalex.org/W2115058083","https://openalex.org/W2132258839","https://openalex.org/W2136348740","https://openalex.org/W2143285027","https://openalex.org/W2149904390","https://openalex.org/W2154556318","https://openalex.org/W2159717773","https://openalex.org/W2166630981","https://openalex.org/W2171006257","https://openalex.org/W2295099251","https://openalex.org/W4237150160","https://openalex.org/W4242258435","https://openalex.org/W4249279097","https://openalex.org/W4251000960","https://openalex.org/W4253065618","https://openalex.org/W4253255368","https://openalex.org/W6636088595","https://openalex.org/W6658501462"],"related_works":["https://openalex.org/W2065759842","https://openalex.org/W2185658074","https://openalex.org/W3008068282","https://openalex.org/W2019238062","https://openalex.org/W2138825797","https://openalex.org/W1707075782","https://openalex.org/W4243618206","https://openalex.org/W2148966412","https://openalex.org/W2102480477","https://openalex.org/W4233816696"],"abstract_inverted_index":{"As":[0],"microprocessor":[1],"speeds":[2],"increase,":[3],"memory":[4,74,116,121,138,155],"bandwidth":[5,62],"is":[6,28],"rapidly":[7],"becoming":[8],"the":[9,13,42,65,73,96,104,125,131,137,154],"performance":[10,22],"bottleneck":[11],"in":[12,147],"execution":[14],"of":[15,44,67,72,115,127,153],"vector-like":[16],"algorithms.":[17],"Although":[18],"caching":[19,26,110],"provides":[20],"adequate":[21],"for":[23,32,98],"many":[24],"problems,":[25],"alone":[27],"an":[29,148],"insufficient":[30],"solution":[31],"vector":[33],"applications":[34],"with":[35,119],"poor":[36],"temporal":[37],"and":[38,82],"spatial":[39],"locality.":[40],"Moreover,":[41],"nature":[43],"memories":[45],"themselves":[46],"has":[47],"changed.":[48],"Current":[49],"DRAM":[50],"components":[51,68],"should":[52],"not":[53],"be":[54,145],"treated":[55],"as":[56],"uniform":[57],"access-time":[58],"RAM:":[59],"achieving":[60],"greater":[61],"requires":[63],"exploiting":[64],"characteristics":[66],"at":[69],"every":[70],"level":[71],"hierarchy.":[75],"The":[76,107],"authors":[77],"describe":[78],"hardware-assisted":[79],"access":[80,117],"ordering":[81],"a":[83,89,99,120],"hardware":[84],"development":[85],"effort":[86],"to":[87,136,144],"build":[88],"Stream":[90],"Memory":[91],"Controller":[92],"(SMC)":[93],"that":[94,123,134,150],"implements":[95],"technique":[97],"commercially":[100],"available":[101],"high-performance":[102],"microprocessor,":[103],"Intel":[105],"i860.":[106],"strategy":[108],"augments":[109],"by":[111,130],"combining":[112],"compile-time":[113],"detection":[114],"patterns":[118],"subsystem":[122],"decouples":[124],"order":[126,149],"requests":[128,143],"generated":[129],"processor":[132],"from":[133],"issued":[135,146],"system.":[139],"This":[140],"decoupling":[141],"permits":[142],"optimizes":[151],"use":[152],"system.<":[156],"<ETX":[157],"xmlns:mml=\"http://www.w3.org/1998/Math/MathML\"":[158],"xmlns:xlink=\"http://www.w3.org/1999/xlink\">&gt;</ETX>":[159]},"counts_by_year":[],"updated_date":"2025-11-06T03:46:38.306776","created_date":"2025-10-10T00:00:00"}