{"id":"https://openalex.org/W3210475641","doi":"https://doi.org/10.1109/hcs52781.2021.9567072","title":"SOT-MRAM \u2013 Third generation MRAM memory opens new opportunities : Hot Chips Conference August 2021","display_name":"SOT-MRAM \u2013 Third generation MRAM memory opens new opportunities : Hot Chips Conference August 2021","publication_year":2021,"publication_date":"2021-08-22","ids":{"openalex":"https://openalex.org/W3210475641","doi":"https://doi.org/10.1109/hcs52781.2021.9567072","mag":"3210475641"},"language":"en","primary_location":{"id":"doi:10.1109/hcs52781.2021.9567072","is_oa":false,"landing_page_url":"https://doi.org/10.1109/hcs52781.2021.9567072","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2021 IEEE Hot Chips 33 Symposium (HCS)","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5051365087","display_name":"Barry Hoberman","orcid":null},"institutions":[],"countries":[],"is_corresponding":true,"raw_author_name":"Barry Hoberman","raw_affiliation_strings":[],"affiliations":[]},{"author_position":"last","author":{"id":"https://openalex.org/A5110902319","display_name":"Jean\u2010Pierre Nozi\u00e8res","orcid":null},"institutions":[{"id":"https://openalex.org/I1294671590","display_name":"Centre National de la Recherche Scientifique","ror":"https://ror.org/02feahw73","country_code":"FR","type":"funder","lineage":["https://openalex.org/I1294671590"]}],"countries":["FR"],"is_corresponding":false,"raw_author_name":"Jean-Pierre Nozieres","raw_affiliation_strings":["CNRS - Centre National de la Recherche Scientifique (France)"],"affiliations":[{"raw_affiliation_string":"CNRS - Centre National de la Recherche Scientifique (France)","institution_ids":["https://openalex.org/I1294671590"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":2,"corresponding_author_ids":["https://openalex.org/A5051365087"],"corresponding_institution_ids":[],"apc_list":null,"apc_paid":null,"fwci":0.1012,"has_fulltext":false,"cited_by_count":2,"citation_normalized_percentile":{"value":0.44921181,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":89,"max":95},"biblio":{"volume":null,"issue":null,"first_page":"1","last_page":"10"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T12808","display_name":"Ferroelectric and Negative Capacitance Devices","score":0.8917999863624573,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T12808","display_name":"Ferroelectric and Negative Capacitance Devices","score":0.8917999863624573,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10472","display_name":"Semiconductor materials and devices","score":0.8579000234603882,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/magnetoresistive-random-access-memory","display_name":"Magnetoresistive random-access memory","score":0.9768732786178589},{"id":"https://openalex.org/keywords/cmos","display_name":"CMOS","score":0.6710258722305298},{"id":"https://openalex.org/keywords/static-random-access-memory","display_name":"Static random-access memory","score":0.6060149073600769},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.4725237488746643},{"id":"https://openalex.org/keywords/universal-memory","display_name":"Universal memory","score":0.4382554590702057},{"id":"https://openalex.org/keywords/visibility","display_name":"Visibility","score":0.42499616742134094},{"id":"https://openalex.org/keywords/random-access-memory","display_name":"Random access memory","score":0.3925546705722809},{"id":"https://openalex.org/keywords/electrical-engineering","display_name":"Electrical engineering","score":0.37265145778656006},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.32692795991897583},{"id":"https://openalex.org/keywords/semiconductor-memory","display_name":"Semiconductor memory","score":0.2873024642467499},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.2831665873527527},{"id":"https://openalex.org/keywords/computer-hardware","display_name":"Computer hardware","score":0.21972787380218506},{"id":"https://openalex.org/keywords/computer-memory","display_name":"Computer memory","score":0.19255834817886353},{"id":"https://openalex.org/keywords/memory-refresh","display_name":"Memory refresh","score":0.12176457047462463},{"id":"https://openalex.org/keywords/physics","display_name":"Physics","score":0.08770111203193665}],"concepts":[{"id":"https://openalex.org/C46891859","wikidata":"https://www.wikidata.org/wiki/Q1061546","display_name":"Magnetoresistive random-access memory","level":3,"score":0.9768732786178589},{"id":"https://openalex.org/C46362747","wikidata":"https://www.wikidata.org/wiki/Q173431","display_name":"CMOS","level":2,"score":0.6710258722305298},{"id":"https://openalex.org/C68043766","wikidata":"https://www.wikidata.org/wiki/Q267416","display_name":"Static random-access memory","level":2,"score":0.6060149073600769},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.4725237488746643},{"id":"https://openalex.org/C195053848","wikidata":"https://www.wikidata.org/wiki/Q7894141","display_name":"Universal memory","level":5,"score":0.4382554590702057},{"id":"https://openalex.org/C123403432","wikidata":"https://www.wikidata.org/wiki/Q654068","display_name":"Visibility","level":2,"score":0.42499616742134094},{"id":"https://openalex.org/C2994168587","wikidata":"https://www.wikidata.org/wiki/Q5295","display_name":"Random access memory","level":2,"score":0.3925546705722809},{"id":"https://openalex.org/C119599485","wikidata":"https://www.wikidata.org/wiki/Q43035","display_name":"Electrical engineering","level":1,"score":0.37265145778656006},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.32692795991897583},{"id":"https://openalex.org/C98986596","wikidata":"https://www.wikidata.org/wiki/Q1143031","display_name":"Semiconductor memory","level":2,"score":0.2873024642467499},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.2831665873527527},{"id":"https://openalex.org/C9390403","wikidata":"https://www.wikidata.org/wiki/Q3966","display_name":"Computer hardware","level":1,"score":0.21972787380218506},{"id":"https://openalex.org/C92855701","wikidata":"https://www.wikidata.org/wiki/Q5830907","display_name":"Computer memory","level":3,"score":0.19255834817886353},{"id":"https://openalex.org/C87907426","wikidata":"https://www.wikidata.org/wiki/Q6815755","display_name":"Memory refresh","level":4,"score":0.12176457047462463},{"id":"https://openalex.org/C121332964","wikidata":"https://www.wikidata.org/wiki/Q413","display_name":"Physics","level":0,"score":0.08770111203193665},{"id":"https://openalex.org/C120665830","wikidata":"https://www.wikidata.org/wiki/Q14620","display_name":"Optics","level":1,"score":0.0}],"mesh":[],"locations_count":2,"locations":[{"id":"doi:10.1109/hcs52781.2021.9567072","is_oa":false,"landing_page_url":"https://doi.org/10.1109/hcs52781.2021.9567072","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2021 IEEE Hot Chips 33 Symposium (HCS)","raw_type":"proceedings-article"},{"id":"pmh:oai:HAL:hal-04735356v1","is_oa":false,"landing_page_url":"https://hal.science/hal-04735356","pdf_url":null,"source":{"id":"https://openalex.org/S4406922461","display_name":"SPIRE - Sciences Po Institutional REpository","issn_l":null,"issn":null,"is_oa":false,"is_in_doaj":false,"is_core":false,"host_organization":null,"host_organization_name":null,"host_organization_lineage":[],"host_organization_lineage_names":[],"type":"repository"},"license":null,"license_id":null,"version":"submittedVersion","is_accepted":false,"is_published":false,"raw_source_name":"2021 IEEE Hot Chips 33 Symposium (HCS), Aug 2021, Palo Alto, United States. pp.1-10, &#x27E8;10.1109/HCS52781.2021.9567072&#x27E9;","raw_type":"Conference papers"}],"best_oa_location":null,"sustainable_development_goals":[{"display_name":"Industry, innovation and infrastructure","id":"https://metadata.un.org/sdg/9","score":0.550000011920929}],"awards":[],"funders":[],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":0,"referenced_works":[],"related_works":["https://openalex.org/W4235980920","https://openalex.org/W1974599144","https://openalex.org/W370196896","https://openalex.org/W2793465010","https://openalex.org/W1998340208","https://openalex.org/W2186356227","https://openalex.org/W3205888584","https://openalex.org/W2441908667","https://openalex.org/W4206753316","https://openalex.org/W2541005978"],"abstract_inverted_index":{"SOT":[0,44,47],"is":[1,48],"a":[2],"straightforward":[3],"extension":[4],"of":[5,43],"today\u2019s":[6],"\u2018in":[7],"production\u2019":[8],"MRAM":[9],"technologies":[10],"running":[11],"in":[12,30,50],"major":[13],"foundries.":[14],"First":[15],"memory":[16],"technology":[17],"to":[18,23,57],"genuinely":[19],"have":[20],"the":[21],"capability":[22],"converge":[24],"both":[25],"SRAM":[26],"and":[27,40],"NVM":[28],"characteristics":[29],"advanced":[31],"CMOS":[32],"nodes":[33],"$(":[34],"\\le":[35],"28$":[36],"nm).":[37],"Power,":[38],"cost,":[39],"performance":[41],"benefits":[42],"are":[45],"compelling.":[46],"still":[49],"development,":[51],"but":[52],"look":[53],"for":[54],"market":[55],"visibility":[56],"begin":[58],"around":[59],"2024":[60]},"counts_by_year":[{"year":2025,"cited_by_count":1},{"year":2023,"cited_by_count":1}],"updated_date":"2026-03-20T23:20:44.827607","created_date":"2025-10-10T00:00:00"}
