{"id":"https://openalex.org/W2147903260","doi":"https://doi.org/10.1109/fpt.2004.1393252","title":"Placement and routing for non-rectangular embedded programmable logic cores in SoC design","display_name":"Placement and routing for non-rectangular embedded programmable logic cores in SoC design","publication_year":2005,"publication_date":"2005-03-21","ids":{"openalex":"https://openalex.org/W2147903260","doi":"https://doi.org/10.1109/fpt.2004.1393252","mag":"2147903260"},"language":"en","primary_location":{"id":"doi:10.1109/fpt.2004.1393252","is_oa":false,"landing_page_url":"https://doi.org/10.1109/fpt.2004.1393252","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Proceedings. 2004 IEEE International Conference on Field- Programmable Technology (IEEE Cat. No.04EX921)","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5061170368","display_name":"Thomas G. Wong","orcid":"https://orcid.org/0000-0002-5019-7302"},"institutions":[{"id":"https://openalex.org/I141945490","display_name":"University of British Columbia","ror":"https://ror.org/03rmrcq20","country_code":"CA","type":"education","lineage":["https://openalex.org/I141945490"]}],"countries":["CA"],"is_corresponding":true,"raw_author_name":"T. Wong","raw_affiliation_strings":["Department of Electrical and Computer Engineering, University of British Columbia, Vancouver, BC, Canada"],"affiliations":[{"raw_affiliation_string":"Department of Electrical and Computer Engineering, University of British Columbia, Vancouver, BC, Canada","institution_ids":["https://openalex.org/I141945490"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5013246362","display_name":"Steven J. E. Wilton","orcid":"https://orcid.org/0000-0002-1241-6690"},"institutions":[{"id":"https://openalex.org/I141945490","display_name":"University of British Columbia","ror":"https://ror.org/03rmrcq20","country_code":"CA","type":"education","lineage":["https://openalex.org/I141945490"]}],"countries":["CA"],"is_corresponding":false,"raw_author_name":"S.J.E. Wilton","raw_affiliation_strings":["Department of Electrical and Computer Engineering, University of British Columbia, Vancouver, BC, Canada"],"affiliations":[{"raw_affiliation_string":"Department of Electrical and Computer Engineering, University of British Columbia, Vancouver, BC, Canada","institution_ids":["https://openalex.org/I141945490"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":2,"corresponding_author_ids":["https://openalex.org/A5061170368"],"corresponding_institution_ids":["https://openalex.org/I141945490"],"apc_list":null,"apc_paid":null,"fwci":1.0883,"has_fulltext":false,"cited_by_count":7,"citation_normalized_percentile":{"value":0.80544971,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":90,"max":94},"biblio":{"volume":null,"issue":null,"first_page":"65","last_page":"72"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T11522","display_name":"VLSI and FPGA Design Techniques","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T11522","display_name":"VLSI and FPGA Design Techniques","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11032","display_name":"VLSI and Analog Circuit Testing","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11527","display_name":"3D IC and TSV technologies","score":0.9997000098228455,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/routing","display_name":"Routing (electronic design automation)","score":0.6128992438316345},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.5832550525665283},{"id":"https://openalex.org/keywords/programmable-logic-device","display_name":"Programmable logic device","score":0.5302426815032959},{"id":"https://openalex.org/keywords/logic-synthesis","display_name":"Logic synthesis","score":0.5037774443626404},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.44628214836120605},{"id":"https://openalex.org/keywords/programmable-logic-array","display_name":"Programmable logic array","score":0.41105154156684875},{"id":"https://openalex.org/keywords/computer-architecture","display_name":"Computer architecture","score":0.3968997299671173},{"id":"https://openalex.org/keywords/logic-gate","display_name":"Logic gate","score":0.38824039697647095},{"id":"https://openalex.org/keywords/parallel-computing","display_name":"Parallel computing","score":0.332187294960022},{"id":"https://openalex.org/keywords/algorithm","display_name":"Algorithm","score":0.06887215375900269}],"concepts":[{"id":"https://openalex.org/C74172769","wikidata":"https://www.wikidata.org/wiki/Q1446839","display_name":"Routing (electronic design automation)","level":2,"score":0.6128992438316345},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.5832550525665283},{"id":"https://openalex.org/C206274596","wikidata":"https://www.wikidata.org/wiki/Q1063837","display_name":"Programmable logic device","level":2,"score":0.5302426815032959},{"id":"https://openalex.org/C157922185","wikidata":"https://www.wikidata.org/wiki/Q173198","display_name":"Logic synthesis","level":3,"score":0.5037774443626404},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.44628214836120605},{"id":"https://openalex.org/C182322920","wikidata":"https://www.wikidata.org/wiki/Q2112217","display_name":"Programmable logic array","level":3,"score":0.41105154156684875},{"id":"https://openalex.org/C118524514","wikidata":"https://www.wikidata.org/wiki/Q173212","display_name":"Computer architecture","level":1,"score":0.3968997299671173},{"id":"https://openalex.org/C131017901","wikidata":"https://www.wikidata.org/wiki/Q170451","display_name":"Logic gate","level":2,"score":0.38824039697647095},{"id":"https://openalex.org/C173608175","wikidata":"https://www.wikidata.org/wiki/Q232661","display_name":"Parallel computing","level":1,"score":0.332187294960022},{"id":"https://openalex.org/C11413529","wikidata":"https://www.wikidata.org/wiki/Q8366","display_name":"Algorithm","level":1,"score":0.06887215375900269}],"mesh":[],"locations_count":2,"locations":[{"id":"doi:10.1109/fpt.2004.1393252","is_oa":false,"landing_page_url":"https://doi.org/10.1109/fpt.2004.1393252","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Proceedings. 2004 IEEE International Conference on Field- Programmable Technology (IEEE Cat. No.04EX921)","raw_type":"proceedings-article"},{"id":"pmh:oai:CiteSeerX.psu:10.1.1.225.6147","is_oa":false,"landing_page_url":"http://citeseerx.ist.psu.edu/viewdoc/summary?doi=10.1.1.225.6147","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"submittedVersion","is_accepted":false,"is_published":false,"raw_source_name":"http://www.ece.ubc.ca/%7Estevew/papers/pdf/fpt2004b.pdf","raw_type":"text"}],"best_oa_location":null,"sustainable_development_goals":[],"awards":[],"funders":[],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":8,"referenced_works":["https://openalex.org/W1523051745","https://openalex.org/W1524957862","https://openalex.org/W2094806828","https://openalex.org/W2105715355","https://openalex.org/W2111756578","https://openalex.org/W2123802188","https://openalex.org/W2139637699","https://openalex.org/W2160474882"],"related_works":["https://openalex.org/W1512285683","https://openalex.org/W4234601000","https://openalex.org/W2139569078","https://openalex.org/W2135636985","https://openalex.org/W2197466303","https://openalex.org/W2187918628","https://openalex.org/W4239388060","https://openalex.org/W1607849496","https://openalex.org/W2170504327","https://openalex.org/W2526300902"],"abstract_inverted_index":{"As":[0],"SoC":[1,37],"design":[2,38],"enters":[3],"into":[4],"mainstream":[5],"usage,":[6],"the":[7,36,63,90,139,150,190,197],"ability":[8,20],"to":[9,59,74,85,131,141,154,183],"make":[10],"post-fabrication":[11],"changes":[12],"will":[13],"become":[14],"more":[15,17],"and":[16,80,94,127,134,163,172],"attractive.":[18],"This":[19],"can":[21,44],"be":[22,45,193],"realized":[23],"using":[24,176],"programmable":[25,53,76,99,124],"logic":[26,54,77,100,125],"cores.":[27,145,169],"These":[28],"cores":[29,55,179],"are":[30,56,83,107],"like":[31],"any":[32],"other":[33,64],"IP":[34,65],"in":[35],"methodology,":[39],"except":[40],"that":[41,97,114,137,149,189],"their":[42],"function":[43],"changed":[46],"after":[47],"fabrication.":[48],"In":[49,72],"many":[50],"cases,":[51],"non-rectangular":[52,123,178],"required,":[57],"either":[58],"better":[60,142],"mesh":[61],"with":[62],"cores,":[66,78,126,162,185],"or":[67,110],"because":[68],"of":[69],"I/O":[70],"constraints.":[71],"order":[73],"use":[75],"placement":[79,93,133],"routing":[81,95,135],"algorithms":[82,96,116,136,140,152,199],"required":[84],"implement":[86],"user":[87],"circuits":[88],"on":[89],"core.":[91],"Existing":[92],"target":[98,143],"were":[101,200],"optimized":[102],"for":[103,160,167,175],"stand-alone":[104],"FPGAs":[105],"which":[106],"invariably":[108],"square":[109,184],"rectangular.":[111],"We":[112],"show":[113,188],"these":[115,144,177],"do":[117],"not":[118],"work":[119],"well":[120],"when":[121],"targetting":[122],"we":[128,187],"present":[129],"enhancements":[130],"existing":[132],"allow":[138],"It":[146],"is":[147,180],"shown":[148],"new":[151],"lead":[153],"a":[155,164],"12%":[156],"critical":[157],"path":[158],"improvement":[159,166],"\"U\"-shaped":[161],"4%":[165],"\"O\"-shaped":[168],"The":[170],"density":[171],"speed":[173],"penalty":[174,191],"significant,":[181],"compared":[182],"however,":[186],"would":[192],"significantly":[194],"larger":[195],"if":[196],"original":[198],"used.":[201]},"counts_by_year":[{"year":2022,"cited_by_count":1},{"year":2014,"cited_by_count":1}],"updated_date":"2026-04-04T16:13:02.066488","created_date":"2025-10-10T00:00:00"}