{"id":"https://openalex.org/W4403279674","doi":"https://doi.org/10.1109/fpl64840.2024.00033","title":"Techniques for Exploring Fine-Grained LUT and Routing Aging on a 28nm FPGA","display_name":"Techniques for Exploring Fine-Grained LUT and Routing Aging on a 28nm FPGA","publication_year":2024,"publication_date":"2024-09-02","ids":{"openalex":"https://openalex.org/W4403279674","doi":"https://doi.org/10.1109/fpl64840.2024.00033"},"language":"en","primary_location":{"id":"doi:10.1109/fpl64840.2024.00033","is_oa":false,"landing_page_url":"https://doi.org/10.1109/fpl64840.2024.00033","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2024 34th International Conference on Field-Programmable Logic and Applications (FPL)","raw_type":"proceedings-article"},"type":"conference-paper","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5009912688","display_name":"Hayden Cook","orcid":"https://orcid.org/0000-0002-1067-0054"},"institutions":[{"id":"https://openalex.org/I100005738","display_name":"Brigham Young University","ror":"https://ror.org/047rhhm47","country_code":"US","type":"education","lineage":["https://openalex.org/I100005738"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Hayden Cook","raw_affiliation_strings":["Brigham Young University,Department of Electrical and Computer Engineering,Provo,Utah,USA"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Brigham Young University,Department of Electrical and Computer Engineering,Provo,Utah,USA","institution_ids":["https://openalex.org/I100005738"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5006132600","display_name":"Jeffrey Goeders","orcid":"https://orcid.org/0000-0002-9822-6926"},"institutions":[{"id":"https://openalex.org/I100005738","display_name":"Brigham Young University","ror":"https://ror.org/047rhhm47","country_code":"US","type":"education","lineage":["https://openalex.org/I100005738"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Jeffrey Goeders","raw_affiliation_strings":["Brigham Young University,Department of Electrical and Computer Engineering,Provo,Utah,USA"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Brigham Young University,Department of Electrical and Computer Engineering,Provo,Utah,USA","institution_ids":["https://openalex.org/I100005738"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":1,"corresponding_author_ids":[],"corresponding_institution_ids":["https://openalex.org/I100005738"],"apc_list":null,"apc_paid":null,"fwci":null,"has_fulltext":false,"cited_by_count":0,"citation_normalized_percentile":null,"cited_by_percentile_year":null,"biblio":{"volume":null,"issue":null,"first_page":"178","last_page":"186"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T11032","display_name":"VLSI and Analog Circuit Testing","score":0.9897000193595886,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T11032","display_name":"VLSI and Analog Circuit Testing","score":0.9897000193595886,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T14117","display_name":"Integrated Circuits and Semiconductor Failure Analysis","score":0.9889000058174133,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10624","display_name":"Silicon and Solar Cell Technologies","score":0.9617999792098999,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/lookup-table","display_name":"Lookup table","score":0.8430240154266357},{"id":"https://openalex.org/keywords/field-programmable-gate-array","display_name":"Field-programmable gate array","score":0.7620835900306702},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.7000293731689453},{"id":"https://openalex.org/keywords/routing","display_name":"Routing (electronic design automation)","score":0.6389936804771423},{"id":"https://openalex.org/keywords/parallel-computing","display_name":"Parallel computing","score":0.47836488485336304},{"id":"https://openalex.org/keywords/computer-architecture","display_name":"Computer architecture","score":0.3862275183200836},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.3234708905220032},{"id":"https://openalex.org/keywords/operating-system","display_name":"Operating system","score":0.07823210954666138}],"concepts":[{"id":"https://openalex.org/C134835016","wikidata":"https://www.wikidata.org/wiki/Q690265","display_name":"Lookup table","level":2,"score":0.8430240154266357},{"id":"https://openalex.org/C42935608","wikidata":"https://www.wikidata.org/wiki/Q190411","display_name":"Field-programmable gate array","level":2,"score":0.7620835900306702},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.7000293731689453},{"id":"https://openalex.org/C74172769","wikidata":"https://www.wikidata.org/wiki/Q1446839","display_name":"Routing (electronic design automation)","level":2,"score":0.6389936804771423},{"id":"https://openalex.org/C173608175","wikidata":"https://www.wikidata.org/wiki/Q232661","display_name":"Parallel computing","level":1,"score":0.47836488485336304},{"id":"https://openalex.org/C118524514","wikidata":"https://www.wikidata.org/wiki/Q173212","display_name":"Computer architecture","level":1,"score":0.3862275183200836},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.3234708905220032},{"id":"https://openalex.org/C111919701","wikidata":"https://www.wikidata.org/wiki/Q9135","display_name":"Operating system","level":1,"score":0.07823210954666138}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/fpl64840.2024.00033","is_oa":false,"landing_page_url":"https://doi.org/10.1109/fpl64840.2024.00033","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2024 34th International Conference on Field-Programmable Logic and Applications (FPL)","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[{"id":"https://metadata.un.org/sdg/2","display_name":"Zero hunger","score":0.5299999713897705}],"awards":[],"funders":[{"id":"https://openalex.org/F4320306076","display_name":"National Science Foundation","ror":"https://ror.org/021nxhr62"}],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":28,"referenced_works":["https://openalex.org/W1600691640","https://openalex.org/W1978921906","https://openalex.org/W2012561239","https://openalex.org/W2053346678","https://openalex.org/W2076930138","https://openalex.org/W2126460857","https://openalex.org/W2135064681","https://openalex.org/W2145810750","https://openalex.org/W2151329817","https://openalex.org/W2164595519","https://openalex.org/W2167583372","https://openalex.org/W2737126661","https://openalex.org/W2891839221","https://openalex.org/W2921944720","https://openalex.org/W3094552862","https://openalex.org/W4311839959","https://openalex.org/W4390110843","https://openalex.org/W6631122486","https://openalex.org/W6655329893","https://openalex.org/W6725080815","https://openalex.org/W6727497952","https://openalex.org/W6727566158","https://openalex.org/W6728283774","https://openalex.org/W6745932936","https://openalex.org/W6758154066","https://openalex.org/W6774598094","https://openalex.org/W6808132911","https://openalex.org/W6857496097"],"related_works":["https://openalex.org/W2117300767","https://openalex.org/W2024574431","https://openalex.org/W2131696304","https://openalex.org/W3146360095","https://openalex.org/W2374017528","https://openalex.org/W4285503609","https://openalex.org/W2126248441","https://openalex.org/W2184011203","https://openalex.org/W1967938402","https://openalex.org/W2386041993"],"abstract_inverted_index":{"Understanding":[0],"how":[1,5,101,140],"FPGAs":[2,19],"age":[3],"and":[4,16,42,65,77,92,133,143],"to":[6,24,35,51,71,83,116],"control":[7,106],"that":[8,80],"aging":[9,37,88,110,120,129,149],"is":[10],"crucial":[11],"for":[12],"ensuring":[13],"the":[14,25,53,85,108,117,148],"reliability":[15],"security":[17],"of":[18,28,55,75,87,107,111,119],"in":[20,95,134],"critical":[21],"applications.":[22],"Due":[23],"proprietary":[26],"nature":[27],"commercial":[29],"FPGAs,":[30],"it":[31],"can":[32,146],"be":[33],"challenging":[34],"validate":[36],"models":[38],"on":[39,48,89],"real":[40],"silicon,":[41],"most":[43],"previous":[44],"work":[45],"has":[46],"relied":[47],"circuit":[49],"simulations":[50],"study":[52],"effects":[54,86],"FPGA":[56,113],"aging.":[57],"In":[58],"this":[59],"work,":[60],"we":[61,138],"leverage":[62],"low-level":[63],"placement":[64],"routing":[66,93],"APIs":[67],"provided":[68],"by":[69,151],"RapidWright":[70],"create":[72],"a":[73,96,124,135],"series":[74],"stressor":[76],"characterization":[78],"circuits":[79],"allow":[81,104],"us":[82],"measure":[84],"individual":[90,121],"LUTs":[91],"resources":[94],"28nm":[97],"FPGA.":[98],"We":[99],"demonstrate":[100],"these":[102],"techniques":[103],"fine-grained":[105],"relative":[109],"different":[112,128,141],"resources,":[114],"even":[115],"point":[118],"paths":[122],"within":[123],"single":[125],"LUT.":[126],"Several":[127],"experiments":[130],"are":[131],"demonstrated,":[132],"cumulative":[136],"test,":[137],"show":[139],"signal":[142],"LUT":[144],"configurations":[145],"influence":[147],"rate":[150],"over":[152],"2x.":[153]},"counts_by_year":[],"updated_date":"2026-07-14T23:27:15.235271","created_date":"2025-10-10T00:00:00"}