{"id":"https://openalex.org/W2114973805","doi":"https://doi.org/10.1109/fpl.2008.4630042","title":"FPGA interconnect sizing using extended logical effort model","display_name":"FPGA interconnect sizing using extended logical effort model","publication_year":2008,"publication_date":"2008-01-01","ids":{"openalex":"https://openalex.org/W2114973805","doi":"https://doi.org/10.1109/fpl.2008.4630042","mag":"2114973805"},"language":"en","primary_location":{"id":"doi:10.1109/fpl.2008.4630042","is_oa":false,"landing_page_url":"https://doi.org/10.1109/fpl.2008.4630042","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2008 International Conference on Field Programmable Logic and Applications","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5100892776","display_name":"Haile Yu","orcid":null},"institutions":[{"id":"https://openalex.org/I177725633","display_name":"Chinese University of Hong Kong","ror":"https://ror.org/00t33hh48","country_code":"CN","type":"education","lineage":["https://openalex.org/I177725633"]}],"countries":["CN"],"is_corresponding":true,"raw_author_name":"Haile Yu","raw_affiliation_strings":["Department of Computer Science and Engineering, Chinese University of Hong Kong, Hong Kong, China","Dept of Comput. Sci. & Eng., Chinese Univ. of Hong Kong, Hong Kong"],"affiliations":[{"raw_affiliation_string":"Department of Computer Science and Engineering, Chinese University of Hong Kong, Hong Kong, China","institution_ids":["https://openalex.org/I177725633"]},{"raw_affiliation_string":"Dept of Comput. Sci. & Eng., Chinese Univ. of Hong Kong, Hong Kong","institution_ids":["https://openalex.org/I177725633"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":1,"corresponding_author_ids":["https://openalex.org/A5100892776"],"corresponding_institution_ids":["https://openalex.org/I177725633"],"apc_list":null,"apc_paid":null,"fwci":0.0,"has_fulltext":false,"cited_by_count":0,"citation_normalized_percentile":{"value":0.134981,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":null,"biblio":{"volume":"6156","issue":null,"first_page":"695","last_page":"696"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11522","display_name":"VLSI and FPGA Design Techniques","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11032","display_name":"VLSI and Analog Circuit Testing","score":0.9998000264167786,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/field-programmable-gate-array","display_name":"Field-programmable gate array","score":0.7109507918357849},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.6816996335983276},{"id":"https://openalex.org/keywords/sizing","display_name":"Sizing","score":0.6080516576766968},{"id":"https://openalex.org/keywords/interconnection","display_name":"Interconnection","score":0.5684254169464111},{"id":"https://openalex.org/keywords/intuition","display_name":"Intuition","score":0.5562352538108826},{"id":"https://openalex.org/keywords/cad","display_name":"CAD","score":0.5252772569656372},{"id":"https://openalex.org/keywords/electronic-engineering","display_name":"Electronic engineering","score":0.4482630491256714},{"id":"https://openalex.org/keywords/computer-architecture","display_name":"Computer architecture","score":0.44110655784606934},{"id":"https://openalex.org/keywords/delay-calculation","display_name":"Delay calculation","score":0.4182385504245758},{"id":"https://openalex.org/keywords/computer-engineering","display_name":"Computer engineering","score":0.3863053023815155},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.3348005414009094},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.15929198265075684},{"id":"https://openalex.org/keywords/engineering-drawing","display_name":"Engineering drawing","score":0.07677656412124634}],"concepts":[{"id":"https://openalex.org/C42935608","wikidata":"https://www.wikidata.org/wiki/Q190411","display_name":"Field-programmable gate array","level":2,"score":0.7109507918357849},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.6816996335983276},{"id":"https://openalex.org/C2777767291","wikidata":"https://www.wikidata.org/wiki/Q1080291","display_name":"Sizing","level":2,"score":0.6080516576766968},{"id":"https://openalex.org/C123745756","wikidata":"https://www.wikidata.org/wiki/Q1665949","display_name":"Interconnection","level":2,"score":0.5684254169464111},{"id":"https://openalex.org/C132010649","wikidata":"https://www.wikidata.org/wiki/Q189222","display_name":"Intuition","level":2,"score":0.5562352538108826},{"id":"https://openalex.org/C194789388","wikidata":"https://www.wikidata.org/wiki/Q17855283","display_name":"CAD","level":2,"score":0.5252772569656372},{"id":"https://openalex.org/C24326235","wikidata":"https://www.wikidata.org/wiki/Q126095","display_name":"Electronic engineering","level":1,"score":0.4482630491256714},{"id":"https://openalex.org/C118524514","wikidata":"https://www.wikidata.org/wiki/Q173212","display_name":"Computer architecture","level":1,"score":0.44110655784606934},{"id":"https://openalex.org/C174086752","wikidata":"https://www.wikidata.org/wiki/Q5253471","display_name":"Delay calculation","level":3,"score":0.4182385504245758},{"id":"https://openalex.org/C113775141","wikidata":"https://www.wikidata.org/wiki/Q428691","display_name":"Computer engineering","level":1,"score":0.3863053023815155},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.3348005414009094},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.15929198265075684},{"id":"https://openalex.org/C199639397","wikidata":"https://www.wikidata.org/wiki/Q1788588","display_name":"Engineering drawing","level":1,"score":0.07677656412124634},{"id":"https://openalex.org/C153349607","wikidata":"https://www.wikidata.org/wiki/Q36649","display_name":"Visual arts","level":1,"score":0.0},{"id":"https://openalex.org/C111472728","wikidata":"https://www.wikidata.org/wiki/Q9471","display_name":"Epistemology","level":1,"score":0.0},{"id":"https://openalex.org/C31258907","wikidata":"https://www.wikidata.org/wiki/Q1301371","display_name":"Computer network","level":1,"score":0.0},{"id":"https://openalex.org/C142362112","wikidata":"https://www.wikidata.org/wiki/Q735","display_name":"Art","level":0,"score":0.0},{"id":"https://openalex.org/C138885662","wikidata":"https://www.wikidata.org/wiki/Q5891","display_name":"Philosophy","level":0,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/fpl.2008.4630042","is_oa":false,"landing_page_url":"https://doi.org/10.1109/fpl.2008.4630042","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2008 International Conference on Field Programmable Logic and Applications","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[{"display_name":"Industry, innovation and infrastructure","id":"https://metadata.un.org/sdg/9","score":0.5799999833106995}],"awards":[],"funders":[],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":6,"referenced_works":["https://openalex.org/W2031336382","https://openalex.org/W2088115909","https://openalex.org/W2125778215","https://openalex.org/W2138840350","https://openalex.org/W2141256464","https://openalex.org/W6680722722"],"related_works":["https://openalex.org/W2375311683","https://openalex.org/W2366062860","https://openalex.org/W2373777250","https://openalex.org/W2353956655","https://openalex.org/W2020653254","https://openalex.org/W2010454064","https://openalex.org/W2352072014","https://openalex.org/W2373416410","https://openalex.org/W2777621569","https://openalex.org/W2101823170"],"abstract_inverted_index":{"The":[0,52],"proposed":[1],"XLE":[2],"model":[3,78],"will":[4,31],"enable":[5],"us":[6],"to":[7,35,65],"calculate":[8],"the":[9,46,70],"delay":[10,77],"of":[11,49,73],"FPGA":[12,96],"interconnect":[13,97],"and":[14,24,56,60,85],"determine":[15],"closed":[16],"form":[17],"expressions":[18],"for":[19],"optimal":[20],"transistor":[21],"size,":[22],"sensitivity":[23],"a":[25,41,76],"minimal":[26],"bound":[27],"on":[28],"delay.":[29,74],"We":[30],"further":[32],"extend":[33],"it":[34],"cover":[36],"process":[37],"variations,":[38],"resulting":[39],"in":[40,82,93],"tool":[42],"that":[43],"can":[44,62,79],"compare":[45],"statistical":[47],"properties":[48],"different":[50],"architectures.":[51],"models":[53,84],"are":[54],"simple":[55],"relatively":[57],"technology":[58],"independent":[59],"hence":[61],"be":[63,80],"used":[64,81],"gain":[66],"better":[67],"intuition":[68],"into":[69],"major":[71],"causes":[72],"Such":[75],"optimization":[83],"CAD":[86],"tools":[87],"as":[88,90],"well":[89],"aid":[91],"designers":[92],"developing":[94],"new":[95],"schemes.":[98]},"counts_by_year":[],"updated_date":"2025-11-06T03:46:38.306776","created_date":"2025-10-10T00:00:00"}
