{"id":"https://openalex.org/W2160001263","doi":"https://doi.org/10.1109/fpga.1997.624623","title":"Implementation of single precision floating point square root on FPGAs","display_name":"Implementation of single precision floating point square root on FPGAs","publication_year":2002,"publication_date":"2002-11-22","ids":{"openalex":"https://openalex.org/W2160001263","doi":"https://doi.org/10.1109/fpga.1997.624623","mag":"2160001263"},"language":"en","primary_location":{"id":"doi:10.1109/fpga.1997.624623","is_oa":false,"landing_page_url":"https://doi.org/10.1109/fpga.1997.624623","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Proceedings. The 5th Annual IEEE Symposium on Field-Programmable Custom Computing Machines Cat. No.97TB100186)","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5100347627","display_name":"Yamin Li","orcid":"https://orcid.org/0000-0002-0069-5629"},"institutions":[{"id":"https://openalex.org/I141591182","display_name":"University of Aizu","ror":"https://ror.org/02pg0e883","country_code":"JP","type":"education","lineage":["https://openalex.org/I141591182"]}],"countries":["JP"],"is_corresponding":false,"raw_author_name":"Yamin Li","raw_affiliation_strings":["Computer Architecture Laboratory, University of Aizu, Aizu-Wakamatsu, Japan"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Computer Architecture Laboratory, University of Aizu, Aizu-Wakamatsu, Japan","institution_ids":["https://openalex.org/I141591182"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5086739768","display_name":"Wanming Chu","orcid":null},"institutions":[{"id":"https://openalex.org/I141591182","display_name":"University of Aizu","ror":"https://ror.org/02pg0e883","country_code":"JP","type":"education","lineage":["https://openalex.org/I141591182"]}],"countries":["JP"],"is_corresponding":false,"raw_author_name":"Wanming Chu","raw_affiliation_strings":["Computer Architecture Laboratory, University of Aizu, Aizu-Wakamatsu, Japan"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Computer Architecture Laboratory, University of Aizu, Aizu-Wakamatsu, Japan","institution_ids":["https://openalex.org/I141591182"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":2,"corresponding_author_ids":[],"corresponding_institution_ids":[],"apc_list":null,"apc_paid":null,"fwci":3.1495,"has_fulltext":false,"cited_by_count":120,"citation_normalized_percentile":{"value":0.92649967,"is_in_top_1_percent":false,"is_in_top_10_percent":true},"cited_by_percentile_year":{"min":94,"max":99},"biblio":{"volume":null,"issue":null,"first_page":"226","last_page":"232"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T11697","display_name":"Numerical Methods and Algorithms","score":0.9998000264167786,"subfield":{"id":"https://openalex.org/subfields/1703","display_name":"Computational Theory and Mathematics"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T11697","display_name":"Numerical Methods and Algorithms","score":0.9998000264167786,"subfield":{"id":"https://openalex.org/subfields/1703","display_name":"Computational Theory and Mathematics"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11034","display_name":"Digital Filter Design and Implementation","score":0.9965000152587891,"subfield":{"id":"https://openalex.org/subfields/1711","display_name":"Signal Processing"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10054","display_name":"Parallel Computing and Optimization Techniques","score":0.9824000000953674,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/square-root","display_name":"Square root","score":0.820520281791687},{"id":"https://openalex.org/keywords/adder","display_name":"Adder","score":0.7540503740310669},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.7099519968032837},{"id":"https://openalex.org/keywords/field-programmable-gate-array","display_name":"Field-programmable gate array","score":0.6786444187164307},{"id":"https://openalex.org/keywords/latency","display_name":"Latency (audio)","score":0.5645425319671631},{"id":"https://openalex.org/keywords/clock-rate","display_name":"Clock rate","score":0.5483310222625732},{"id":"https://openalex.org/keywords/throughput","display_name":"Throughput","score":0.5299160480499268},{"id":"https://openalex.org/keywords/parallel-computing","display_name":"Parallel computing","score":0.5278893709182739},{"id":"https://openalex.org/keywords/floating-point","display_name":"Floating point","score":0.492991179227829},{"id":"https://openalex.org/keywords/low-latency","display_name":"Low latency (capital markets)","score":0.469127893447876},{"id":"https://openalex.org/keywords/computer-hardware","display_name":"Computer hardware","score":0.3509984016418457},{"id":"https://openalex.org/keywords/arithmetic","display_name":"Arithmetic","score":0.32978662848472595},{"id":"https://openalex.org/keywords/algorithm","display_name":"Algorithm","score":0.3018707036972046},{"id":"https://openalex.org/keywords/mathematics","display_name":"Mathematics","score":0.15644830465316772},{"id":"https://openalex.org/keywords/chip","display_name":"Chip","score":0.11993947625160217},{"id":"https://openalex.org/keywords/telecommunications","display_name":"Telecommunications","score":0.06326541304588318}],"concepts":[{"id":"https://openalex.org/C11577676","wikidata":"https://www.wikidata.org/wiki/Q134237","display_name":"Square root","level":2,"score":0.820520281791687},{"id":"https://openalex.org/C164620267","wikidata":"https://www.wikidata.org/wiki/Q376953","display_name":"Adder","level":3,"score":0.7540503740310669},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.7099519968032837},{"id":"https://openalex.org/C42935608","wikidata":"https://www.wikidata.org/wiki/Q190411","display_name":"Field-programmable gate array","level":2,"score":0.6786444187164307},{"id":"https://openalex.org/C82876162","wikidata":"https://www.wikidata.org/wiki/Q17096504","display_name":"Latency (audio)","level":2,"score":0.5645425319671631},{"id":"https://openalex.org/C178693496","wikidata":"https://www.wikidata.org/wiki/Q911691","display_name":"Clock rate","level":3,"score":0.5483310222625732},{"id":"https://openalex.org/C157764524","wikidata":"https://www.wikidata.org/wiki/Q1383412","display_name":"Throughput","level":3,"score":0.5299160480499268},{"id":"https://openalex.org/C173608175","wikidata":"https://www.wikidata.org/wiki/Q232661","display_name":"Parallel computing","level":1,"score":0.5278893709182739},{"id":"https://openalex.org/C84211073","wikidata":"https://www.wikidata.org/wiki/Q117879","display_name":"Floating point","level":2,"score":0.492991179227829},{"id":"https://openalex.org/C46637626","wikidata":"https://www.wikidata.org/wiki/Q6693015","display_name":"Low latency (capital markets)","level":2,"score":0.469127893447876},{"id":"https://openalex.org/C9390403","wikidata":"https://www.wikidata.org/wiki/Q3966","display_name":"Computer hardware","level":1,"score":0.3509984016418457},{"id":"https://openalex.org/C94375191","wikidata":"https://www.wikidata.org/wiki/Q11205","display_name":"Arithmetic","level":1,"score":0.32978662848472595},{"id":"https://openalex.org/C11413529","wikidata":"https://www.wikidata.org/wiki/Q8366","display_name":"Algorithm","level":1,"score":0.3018707036972046},{"id":"https://openalex.org/C33923547","wikidata":"https://www.wikidata.org/wiki/Q395","display_name":"Mathematics","level":0,"score":0.15644830465316772},{"id":"https://openalex.org/C165005293","wikidata":"https://www.wikidata.org/wiki/Q1074500","display_name":"Chip","level":2,"score":0.11993947625160217},{"id":"https://openalex.org/C76155785","wikidata":"https://www.wikidata.org/wiki/Q418","display_name":"Telecommunications","level":1,"score":0.06326541304588318},{"id":"https://openalex.org/C2524010","wikidata":"https://www.wikidata.org/wiki/Q8087","display_name":"Geometry","level":1,"score":0.0},{"id":"https://openalex.org/C555944384","wikidata":"https://www.wikidata.org/wiki/Q249","display_name":"Wireless","level":2,"score":0.0},{"id":"https://openalex.org/C31258907","wikidata":"https://www.wikidata.org/wiki/Q1301371","display_name":"Computer network","level":1,"score":0.0}],"mesh":[],"locations_count":3,"locations":[{"id":"doi:10.1109/fpga.1997.624623","is_oa":false,"landing_page_url":"https://doi.org/10.1109/fpga.1997.624623","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Proceedings. The 5th Annual IEEE Symposium on Field-Programmable Custom Computing Machines Cat. No.97TB100186)","raw_type":"proceedings-article"},{"id":"pmh:oai:CiteSeerX.psu:10.1.1.24.295","is_oa":false,"landing_page_url":"http://citeseerx.ist.psu.edu/viewdoc/summary?doi=10.1.1.24.295","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"submittedVersion","is_accepted":false,"is_published":false,"raw_source_name":"http://wwwcis.k.hosei.ac.jp/~yamin/papers/FCCM97.ps","raw_type":"text"},{"id":"pmh:oai:CiteSeerX.psu:10.1.1.46.9692","is_oa":false,"landing_page_url":"http://citeseerx.ist.psu.edu/viewdoc/summary?doi=10.1.1.46.9692","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"submittedVersion","is_accepted":false,"is_published":false,"raw_source_name":"http://www.u-aizu.ac.jp/~yamin/research/FCCM97.ps.Z","raw_type":"text"}],"best_oa_location":null,"sustainable_development_goals":[],"awards":[],"funders":[],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":19,"referenced_works":["https://openalex.org/W1555915743","https://openalex.org/W1608010962","https://openalex.org/W1944073140","https://openalex.org/W1972470771","https://openalex.org/W1978293337","https://openalex.org/W2006431937","https://openalex.org/W2014125237","https://openalex.org/W2023462640","https://openalex.org/W2062297547","https://openalex.org/W2074838321","https://openalex.org/W2100278660","https://openalex.org/W2108779609","https://openalex.org/W2120978237","https://openalex.org/W2146186061","https://openalex.org/W2165253548","https://openalex.org/W2171048434","https://openalex.org/W2172800476","https://openalex.org/W2725179571","https://openalex.org/W6640535786"],"related_works":["https://openalex.org/W4390550886","https://openalex.org/W3037505396","https://openalex.org/W3200055559","https://openalex.org/W2070160710","https://openalex.org/W1895318900","https://openalex.org/W162485434","https://openalex.org/W2743067409","https://openalex.org/W2124998302","https://openalex.org/W2124904625","https://openalex.org/W2365433197"],"abstract_inverted_index":{"The":[0,54,69,79],"square":[1,24,35,105],"root":[2,25,36,106],"operation":[3,55,80],"is":[4,45,57,65,71,82,90,100],"hard":[5],"to":[6],"implement":[7],"on":[8,39,42,108],"FPGAs":[9],"because":[10],"of":[11,14,102],"the":[12,15,40,62,87,97],"complexity":[13],"algorithms.":[16],"In":[17],"this":[18],"paper,":[19],"we":[20],"present":[21],"a":[22,51,104],"non-restoring":[23],"algorithm":[26,41],"and":[27,61,86],"two":[28],"very":[29],"simple":[30],"single":[31],"precision":[32],"floating":[33],"point":[34],"implementations":[37],"based":[38],"FPGAs.":[43],"One":[44],"low-cost":[46],"iterative":[47],"implementation":[48,74,99],"that":[49,75,96],"uses":[50,76],"traditional":[52],"adder/subtracter.":[53],"latency":[56,81],"25":[58],"clock":[59,67,84,92,110],"cycles":[60,85],"issue":[63,88],"rate":[64,89],"24":[66],"cycles.":[68],"other":[70],"high-throughput":[72],"pipelined":[73,98],"multiple":[77],"adder/subtracters.":[78],"15":[83],"one":[91],"cycle.":[93,111],"It":[94],"means":[95],"capable":[101],"accepting":[103],"instruction":[107],"every":[109]},"counts_by_year":[{"year":2024,"cited_by_count":4},{"year":2023,"cited_by_count":2},{"year":2022,"cited_by_count":5},{"year":2021,"cited_by_count":2},{"year":2020,"cited_by_count":4},{"year":2019,"cited_by_count":4},{"year":2018,"cited_by_count":7},{"year":2017,"cited_by_count":10},{"year":2016,"cited_by_count":8},{"year":2015,"cited_by_count":11},{"year":2014,"cited_by_count":7},{"year":2013,"cited_by_count":9},{"year":2012,"cited_by_count":5}],"updated_date":"2026-06-11T09:08:48.828518","created_date":"2025-10-10T00:00:00"}
