{"id":"https://openalex.org/W7164186167","doi":"https://doi.org/10.1109/fccm68464.2026.00070","title":"Combining HLS and Computation Coding for Balanced Matrix-Vector Engines on FPGA","display_name":"Combining HLS and Computation Coding for Balanced Matrix-Vector Engines on FPGA","publication_year":2026,"publication_date":"2026-05-13","ids":{"openalex":"https://openalex.org/W7164186167","doi":"https://doi.org/10.1109/fccm68464.2026.00070"},"language":null,"primary_location":{"id":"doi:10.1109/fccm68464.2026.00070","is_oa":false,"landing_page_url":"https://doi.org/10.1109/fccm68464.2026.00070","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2026 IEEE 34th Annual International Symposium on Field-Programmable Custom Computing Machines (FCCM)","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5136594032","display_name":"Sayanti Pal","orcid":"https://orcid.org/0009-0001-5016-8325"},"institutions":[{"id":"https://openalex.org/I4665924","display_name":"University of Rostock","ror":"https://ror.org/03zdwsf69","country_code":"DE","type":"education","lineage":["https://openalex.org/I4665924"]}],"countries":["DE"],"is_corresponding":false,"raw_author_name":"Sayanti Pal","raw_affiliation_strings":["University of Rostock,Rostock,Germany"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"University of Rostock,Rostock,Germany","institution_ids":["https://openalex.org/I4665924"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5002123246","display_name":"Alexander Lehnert","orcid":"https://orcid.org/0000-0001-5111-4620"},"institutions":[{"id":"https://openalex.org/I4665924","display_name":"University of Rostock","ror":"https://ror.org/03zdwsf69","country_code":"DE","type":"education","lineage":["https://openalex.org/I4665924"]}],"countries":["DE"],"is_corresponding":false,"raw_author_name":"Alexander Lehnert","raw_affiliation_strings":["University of Rostock,Rostock,Germany"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"University of Rostock,Rostock,Germany","institution_ids":["https://openalex.org/I4665924"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5014794132","display_name":"Marc Reichenbach","orcid":"https://orcid.org/0000-0002-9687-6247"},"institutions":[{"id":"https://openalex.org/I4665924","display_name":"University of Rostock","ror":"https://ror.org/03zdwsf69","country_code":"DE","type":"education","lineage":["https://openalex.org/I4665924"]}],"countries":["DE"],"is_corresponding":false,"raw_author_name":"Marc Reichenbach","raw_affiliation_strings":["University of Rostock,Rostock,Germany"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"University of Rostock,Rostock,Germany","institution_ids":["https://openalex.org/I4665924"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":1,"corresponding_author_ids":[],"corresponding_institution_ids":["https://openalex.org/I4665924"],"apc_list":null,"apc_paid":null,"fwci":0.0,"has_fulltext":false,"cited_by_count":0,"citation_normalized_percentile":{"value":0.84970011,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":null,"biblio":{"volume":null,"issue":null,"first_page":"282","last_page":"282"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T11034","display_name":"Digital Filter Design and Implementation","score":0.2093999981880188,"subfield":{"id":"https://openalex.org/subfields/1711","display_name":"Signal Processing"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T11034","display_name":"Digital Filter Design and Implementation","score":0.2093999981880188,"subfield":{"id":"https://openalex.org/subfields/1711","display_name":"Signal Processing"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10904","display_name":"Embedded Systems Design Techniques","score":0.1671999990940094,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11697","display_name":"Numerical Methods and Algorithms","score":0.16689999401569366,"subfield":{"id":"https://openalex.org/subfields/1703","display_name":"Computational Theory and Mathematics"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/computation","display_name":"Computation","score":0.5379999876022339},{"id":"https://openalex.org/keywords/field-programmable-gate-array","display_name":"Field-programmable gate array","score":0.5023999810218811},{"id":"https://openalex.org/keywords/coding","display_name":"Coding (social sciences)","score":0.4438999891281128},{"id":"https://openalex.org/keywords/decoding-methods","display_name":"Decoding methods","score":0.24969999492168427}],"concepts":[{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.661300003528595},{"id":"https://openalex.org/C45374587","wikidata":"https://www.wikidata.org/wiki/Q12525525","display_name":"Computation","level":2,"score":0.5379999876022339},{"id":"https://openalex.org/C42935608","wikidata":"https://www.wikidata.org/wiki/Q190411","display_name":"Field-programmable gate array","level":2,"score":0.5023999810218811},{"id":"https://openalex.org/C179518139","wikidata":"https://www.wikidata.org/wiki/Q5140297","display_name":"Coding (social sciences)","level":2,"score":0.4438999891281128},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.3637999892234802},{"id":"https://openalex.org/C9390403","wikidata":"https://www.wikidata.org/wiki/Q3966","display_name":"Computer hardware","level":1,"score":0.30959999561309814},{"id":"https://openalex.org/C11413529","wikidata":"https://www.wikidata.org/wiki/Q8366","display_name":"Algorithm","level":1,"score":0.302700012922287},{"id":"https://openalex.org/C173608175","wikidata":"https://www.wikidata.org/wiki/Q232661","display_name":"Parallel computing","level":1,"score":0.2757999897003174},{"id":"https://openalex.org/C57273362","wikidata":"https://www.wikidata.org/wiki/Q576722","display_name":"Decoding methods","level":2,"score":0.24969999492168427},{"id":"https://openalex.org/C142962650","wikidata":"https://www.wikidata.org/wiki/Q240838","display_name":"Reconfigurable computing","level":3,"score":0.249099999666214}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/fccm68464.2026.00070","is_oa":false,"landing_page_url":"https://doi.org/10.1109/fccm68464.2026.00070","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2026 IEEE 34th Annual International Symposium on Field-Programmable Custom Computing Machines (FCCM)","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[],"awards":[],"funders":[],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":1,"referenced_works":["https://openalex.org/W4313555301"],"related_works":[],"abstract_inverted_index":{"Limited":[0],"number":[1],"of":[2,11],"DSP48":[3],"blocks":[4],"versus":[5],"abundant":[6],"LUTs":[7,30],"constrains":[8],"the":[9],"throughput":[10],"FPGA-based":[12],"constant":[13],"matrix\u2013vector":[14],"multiplications":[15],"(MVM).":[16],"We":[17],"exploit":[18],"Linear":[19],"Computation-Coding":[20],"(LCC)":[21],"to":[22],"build":[23],"multiplier-less,":[24],"deeply":[25],"pipelined":[26],"adder":[27],"graphs":[28],"on":[29,62],"and":[31,50],"combine":[32],"it":[33],"with":[34],"a":[35,40,58],"DSP-mapped":[36],"HLS":[37],"datapath":[38],"via":[39],"pragmatic":[41],"column-split":[42],"partition.":[43],"This":[44],"hybrid":[45],"mapping":[46],"achieves":[47],"balanced":[48],"DSP":[49],"LUT":[51],"utilization":[52],"without":[53],"sacrificing":[54],"throughput,":[55],"resulting":[56],"in":[57],"scalable,":[59],"high-performance":[60],"MVM":[61],"FPGAs.":[63]},"counts_by_year":[],"updated_date":"2026-06-26T08:34:08.712188","created_date":"2026-06-11T00:00:00"}