{"id":"https://openalex.org/W7164191887","doi":"https://doi.org/10.1109/fccm68464.2026.00053","title":"DTCore: A Compiler-Directed Control-Minimal FPGA Compute Engine","display_name":"DTCore: A Compiler-Directed Control-Minimal FPGA Compute Engine","publication_year":2026,"publication_date":"2026-05-13","ids":{"openalex":"https://openalex.org/W7164191887","doi":"https://doi.org/10.1109/fccm68464.2026.00053"},"language":null,"primary_location":{"id":"doi:10.1109/fccm68464.2026.00053","is_oa":false,"landing_page_url":"https://doi.org/10.1109/fccm68464.2026.00053","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2026 IEEE 34th Annual International Symposium on Field-Programmable Custom Computing Machines (FCCM)","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5065587135","display_name":"Wei-cheng Zeng","orcid":null},"institutions":[{"id":"https://openalex.org/I118292597","display_name":"National Taipei University of Technology","ror":"https://ror.org/00cn92c09","country_code":"TW","type":"education","lineage":["https://openalex.org/I118292597"]}],"countries":["TW"],"is_corresponding":false,"raw_author_name":"Wei-Cheng Zeng","raw_affiliation_strings":["National Taipei University of Technology,Department of Electronic Engineering,Taipei,Taiwan"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"National Taipei University of Technology,Department of Electronic Engineering,Taipei,Taiwan","institution_ids":["https://openalex.org/I118292597"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5030271774","display_name":"Kuan-Ting Lai","orcid":"https://orcid.org/0000-0002-8497-1562"},"institutions":[{"id":"https://openalex.org/I118292597","display_name":"National Taipei University of Technology","ror":"https://ror.org/00cn92c09","country_code":"TW","type":"education","lineage":["https://openalex.org/I118292597"]}],"countries":["TW"],"is_corresponding":false,"raw_author_name":"Kuan-Ting Lai","raw_affiliation_strings":["National Taipei University of Technology,Department of Electronic Engineering,Taipei,Taiwan"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"National Taipei University of Technology,Department of Electronic Engineering,Taipei,Taiwan","institution_ids":["https://openalex.org/I118292597"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":1,"corresponding_author_ids":[],"corresponding_institution_ids":["https://openalex.org/I118292597"],"apc_list":null,"apc_paid":null,"fwci":0.0,"has_fulltext":false,"cited_by_count":0,"citation_normalized_percentile":{"value":0.85672257,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":null,"biblio":{"volume":null,"issue":null,"first_page":"265","last_page":"265"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10904","display_name":"Embedded Systems Design Techniques","score":0.46889999508857727,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10904","display_name":"Embedded Systems Design Techniques","score":0.46889999508857727,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11697","display_name":"Numerical Methods and Algorithms","score":0.1534000039100647,"subfield":{"id":"https://openalex.org/subfields/1703","display_name":"Computational Theory and Mathematics"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10054","display_name":"Parallel Computing and Optimization Techniques","score":0.12680000066757202,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/field-programmable-gate-array","display_name":"Field-programmable gate array","score":0.3409000039100647},{"id":"https://openalex.org/keywords/noise","display_name":"Noise (video)","score":0.2973000109195709},{"id":"https://openalex.org/keywords/software","display_name":"Software","score":0.2639000117778778},{"id":"https://openalex.org/keywords/key","display_name":"Key (lock)","score":0.2493000030517578},{"id":"https://openalex.org/keywords/set","display_name":"Set (abstract data type)","score":0.24729999899864197}],"concepts":[{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.5778999924659729},{"id":"https://openalex.org/C42935608","wikidata":"https://www.wikidata.org/wiki/Q190411","display_name":"Field-programmable gate array","level":2,"score":0.3409000039100647},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.3021000027656555},{"id":"https://openalex.org/C99498987","wikidata":"https://www.wikidata.org/wiki/Q2210247","display_name":"Noise (video)","level":3,"score":0.2973000109195709},{"id":"https://openalex.org/C2777904410","wikidata":"https://www.wikidata.org/wiki/Q7397","display_name":"Software","level":2,"score":0.2639000117778778},{"id":"https://openalex.org/C9390403","wikidata":"https://www.wikidata.org/wiki/Q3966","display_name":"Computer hardware","level":1,"score":0.258899986743927},{"id":"https://openalex.org/C79403827","wikidata":"https://www.wikidata.org/wiki/Q3988","display_name":"Real-time computing","level":1,"score":0.25119999051094055},{"id":"https://openalex.org/C26517878","wikidata":"https://www.wikidata.org/wiki/Q228039","display_name":"Key (lock)","level":2,"score":0.2493000030517578},{"id":"https://openalex.org/C177264268","wikidata":"https://www.wikidata.org/wiki/Q1514741","display_name":"Set (abstract data type)","level":2,"score":0.24729999899864197},{"id":"https://openalex.org/C18762648","wikidata":"https://www.wikidata.org/wiki/Q42213","display_name":"Work (physics)","level":2,"score":0.23880000412464142}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/fccm68464.2026.00053","is_oa":false,"landing_page_url":"https://doi.org/10.1109/fccm68464.2026.00053","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2026 IEEE 34th Annual International Symposium on Field-Programmable Custom Computing Machines (FCCM)","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[],"awards":[],"funders":[{"id":"https://openalex.org/F4320331164","display_name":"National Science and Technology Council","ror":"https://ror.org/00wnb9798"}],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":2,"referenced_works":["https://openalex.org/W4404102106","https://openalex.org/W4416341766"],"related_works":[],"abstract_inverted_index":{"Structured":[0],"sparsity":[1],"enables":[2],"reduced":[3],"runtime":[4],"orchestration":[5],"on":[6],"FPGAs.":[7],"We":[8],"present":[9],"DTCore,":[10],"a":[11,60],"PC-less,":[12],"compiler-directed":[13],"compute":[14],"engine.":[15],"It":[16],"consumes":[17],"pre-scheduled":[18],"128-bit":[19],"VLIW":[20],"bundles,":[21],"eliminating":[22],"complex":[23],"instruction":[24],"fetch":[25],"and":[26,33],"dynamic":[27],"arbitration.":[28],"Using":[29],"interleaved":[30],"multi-threading":[31],"(IMT)":[32],"explicit":[34],"barriers,":[35],"DTCore":[36],"ensures":[37],"deterministic":[38],"synchronization.":[39],"A":[40],"Xilinx":[41],"ZCU102":[42],"prototype":[43],"closes":[44],"timing":[45],"at":[46],"400":[47],"MHz":[48],"with":[49],"fewer":[50],"than":[51],"10k":[52],"LUTs.":[53],"Overall,":[54],"offloading":[55],"control":[56],"to":[57],"compile-time":[58],"yields":[59],"remarkably":[61],"lightweight,":[62],"high-frequency":[63],"FPGA":[64],"accelerator.":[65]},"counts_by_year":[],"updated_date":"2026-06-26T08:34:08.712188","created_date":"2026-06-11T00:00:00"}